36 lines
1.6 KiB
Systemverilog
36 lines
1.6 KiB
Systemverilog
`ifndef CONTROL_UNIT_H
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`define CONTROL_UNIT_H
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`include "instruction_classifier.sv"
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module control_unit (
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input logic [5:0] op, input logic [5:0] func,
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output logic [0:0] M2R, // Enables writing data stored in memory at the address (rs/A)+(ALU_SRC ? imm : rt/B) into rd
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output logic [0:0] M2W, // Enable writing data stored in rt/B into memory at the address (rs/A)+(ALU_SRC ? imm : rt/B)
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output logic [0:0] B, // AND'ed with flags to determine if branch is permitted
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output logic [3:0] ALU_FN, // Controls what function the ALU is to perform
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output logic [0:0] ALU_SRC, // Controls whether to use the rt/B register read port or 16-bit immediate
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output logic [0:0] RDST, // Controls where to look in the instruction encoding for the register write address
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output logic [0:0] RW // Enable register write port
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);
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logic [0:0] TYPE_R;
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logic [0:0] TYPE_B1;
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logic [0:0] TYPE_J;
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logic [0:0] TYPE_B2;
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logic [0:0] TYPE_I;
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logic [0:0] TYPE_F;
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logic [0:0] TYPE_M;
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instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
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always_comb begin
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M2R = TYPE_M & op[3];
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M2W = TYPE_M & ~op[3];
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B = TYPE_B1 | TYPE_B2 | TYPE_J;
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ALU_FN = (func & {(6){TYPE_R}}) | ( {4'b0000, op[1:0]} & {(6){TYPE_I}});
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ALU_SRC = TYPE_B1 | TYPE_B2 | TYPE_I | TYPE_M;
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RDST = TYPE_I; // Imm ops store back into rt
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RW = TYPE_R | TYPE_I | (TYPE_M & op[3]); // All ALU R-type ops, Addi/Addiu ops, and memory loads
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end
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endmodule
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`endif |