21 lines
438 B
Systemverilog
21 lines
438 B
Systemverilog
`ifndef INSTRUCTION_COUNTER_H
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`define INSTRUCTION_COUNTER_H
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module instruction_counter #(parameter width=5)(
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input logic [0:0] clk, input logic [0:0] we,
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input logic [2**width-1:0] W,
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output logic [2**width-1:0] addr
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);
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logic [2**width-1:0] pc;
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always_ff (@posedge clk) begin
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if (we) begin
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pc <= W
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else
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pc <= pc + 4;
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end
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end
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assign addr = pc;
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endmodule
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`endif |