21 lines
853 B
Systemverilog
21 lines
853 B
Systemverilog
`ifndef INSTRUCTION_CLASSIFIER_H_SV
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`define INSTRUCTION_CLASSIFIER_H_SV
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module instruction_classifier(input logic[5:0] op,
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output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
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output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
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output logic[0:0] M);
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always_comb begin
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// Performs a rolling equals check
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// Uses an AND mask to mask off bits we don't care about
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// And a equals operator to perform a bitwise XNOR followed by a horizontal AND
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R = ( (op & 6'b111111) == 6'b000000);
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B1= ( (op & 6'b111111) == 6'b000001);
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J = ( (op & 6'b111110) == 6'b000010);
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B2= ( (op & 6'b111100) == 6'b000100);
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I = ( (op & 6'b111000) == 6'b001000);
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F = ( (op & 6'b110000) == 6'b010000);
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M = ( (op & 6'b100000) == 6'b100000);
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end
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endmodule
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`endif |