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FPGA_Uni
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assignment-1-submission
FPGA_Uni
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Quartus
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A1_Q1
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simulation
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questa
T
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History
TroubleElectrical
afa8d9d4db
Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments
2026-09-15 21:08:40 +10:00
..
seven_seg.sft
Including quartus prime lite edition project folders for flashing the project to the board
2026-09-03 16:34:31 +10:00
seven_seg.svo
Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments
2026-09-15 21:08:40 +10:00