Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/control_unit.sv

@@ -4,10 +4,13 @@
 
 module control_unit (
     input logic [5:0] op, input logic [5:0] func,
-    output logic [0:0] M2R, output logic [0:0] M2W,
+    output logic [0:0] M2R,     //  Enables writing data stored in memory at the address (rs/A)+(ALU_SRC ? imm : rt/B) into rd
-    output logic [0:0] B,
+    output logic [0:0] M2W,     //  Enable writing data stored in rt/B into memory at the address (rs/A)+(ALU_SRC ? imm : rt/B)
-    output logic [3:0] ALU_FN, output logic [0:0] ALU_SRC,
+    output logic [0:0] B,       //  AND'ed with flags to determine if branch is permitted
-    output logic [0:0] RDST, output logic [0:0] RW
+    output logic [3:0] ALU_FN,  //  Controls what function the ALU is to perform
+    output logic [0:0] ALU_SRC, //  Controls whether to use the rt/B register read port or 16-bit immediate 
+    output logic [0:0] RDST,    //  Controls where to look in the instruction encoding for the register write address
+    output logic [0:0] RW       //  Enable register write port
 );
     logic [0:0] TYPE_R;
     logic [0:0] TYPE_B1;
@@ -20,7 +23,13 @@ module control_unit (
     instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
 
     always_comb begin
-       // TODO 
+        M2R = TYPE_M & op[3];
+        M2W = TYPE_M & ~op[3];
+        B = TYPE_B1 | TYPE_B2 | TYPE_J;
+        ALU_FN = (func & {(6){TYPE_R}}) | ( {4'b0000, op[1:0]} & {(6){TYPE_I}});
+        ALU_SRC = TYPE_B1 | TYPE_B2 | TYPE_I | TYPE_M;
+        RDST = TYPE_I;  // Imm ops store back into rt
+        RW = TYPE_R | TYPE_I | (TYPE_M & op[3]); // All ALU R-type ops, Addi/Addiu ops, and memory loads
     end
 
 endmodule