Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/assignment2.sv

@@ -5,8 +5,7 @@
 `include "ram.sv"
 `include "register_file.sv"
 `include "instruction_counter.sv"
-`include "instruction_classifier.sv"
+`include "control_unit.sv"
-`include "instruction_module_classifier.sv"
 `include "alu.sv"
 `include "shifter.sv"
 `include "sign_extender.sv"
@@ -37,19 +36,13 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] instruction;
 	
 	// Instruction Classifier Intermediates
-	logic[0:0] R;
+	logic [0:0] M2R;
-	logic[0:0] B1;
+	logic [0:0] M2W;
-	logic[0:0] J;
+    logic [0:0] B;
-	logic[0:0] B2;
+    logic [3:0] ALU_FN;
-	logic[0:0] I;
+	logic [0:0] ALU_SRC;
-	logic[0:0] F;
+    logic [0:0] RDST;
-	logic[0:0] M;
+	logic [0:0] RW;
-	
-	// Instruction Module Classifier intermediates	
-	logic [0:0] en_shifter;
-	logic [0:0] en_jmp;
-	logic [0:0] en_mul;
-	logic [0:0] en_alu;
 		
 	// Register File intermediates
 	logic [2:0] flags;
@@ -64,21 +57,16 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	rom #(romsz, 2**width) ROM (pc_addr, instruction);
 
 	logic [2**width-1:0] rd_mem;
-	ram #(ramsz, 2**width) RAM (clk, rd_alu, B1, rt, rd_mem);
+	ram #(ramsz, 2**width) RAM (clk, rd_alu, M2W, rt, rd_mem);
 	
-	instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M);
+	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
-	
+		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
-	instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], 
-		en_shifter, 
-		en_jmp, 
-		en_mul, 
-		en_alu
 	);
 
 
 	register_file #(width, 5) REGS (
 		clk, rd_we, 
-		(F) ? instruction[15:11] : instruction[20:16], rs,
+		(RDST) ? instruction[15:11] : instruction[20:16], rs,
 		instruction[25:21], rt, 
 		instruction[20:16], rd,
 		regs_out
@@ -92,12 +80,13 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 
 	logic [2**width-1:0] rd_alu;
 	logic [2**width-1:0] rt_alu;
-	alu #(width) ALU (instruction[3:0], rs, rt_alu, rd_alu, flags[1:0]);
+	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
-    assign rt_alu = (I) ? (rt_imm) : (rt);
+    assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);
 
-	assign rd_we = M;
+	assign pc_we = B & flags[2];
-	assign pc_we = B1 & flags[2];
 	assign pc_addr_write = (rt_imm << 2) + pc_addr;
+	assign rd_we = RW;
+	assign rd = (M2R) ? rd_alu : rd_mem;
 
 
 

modules/control_unit.sv

@@ -0,0 +1,27 @@
+`ifndef CONTROL_UNIT_H
+`define CONTROL_UNIT_H
+`include "instruction_classifier.sv"
+
+module control_unit (
+    input logic [5:0] op, input logic [5:0] func,
+    output logic [0:0] M2R, output logic [0:0] M2W,
+    output logic [0:0] B,
+    output logic [3:0] ALU_FN, output logic [0:0] ALU_SRC,
+    output logic [0:0] RDST, output logic [0:0] RW
+);
+    logic [0:0] TYPE_R;
+    logic [0:0] TYPE_B1;
+    logic [0:0] TYPE_J;
+    logic [0:0] TYPE_B2;
+    logic [0:0] TYPE_I;
+    logic [0:0] TYPE_F;
+    logic [0:0] TYPE_M;
+
+    instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
+
+    always_comb begin
+       // TODO 
+    end
+
+endmodule;
+`endif

modules/instruction_module_classifier.sv

@@ -1,18 +0,0 @@
-`ifndef INSTRUCTION_MODULE_CLASSIFIER_H_SV
-`define INSTRUCTION_MODULE_CLASSIFIER_H_SV
-
-module instruction_module_classifier(
-    input logic [2:0] op,
-    output logic en_shifter,
-    output logic en_jmp,
-    output logic en_mul,
-    output logic en_alu
-);
-    always_comb begin
-        en_shifter = (op & 3'b111) == 3'b000;
-        en_jmp = (op & 3'b111) == 3'b001;
-        en_mul = (op & 3'b110) == 3'b010;
-        en_alu = (op & 3'b100) == 3'b100;
-    end
-endmodule
-`endif