27 lines
685 B
Systemverilog
27 lines
685 B
Systemverilog
`ifndef CONTROL_UNIT_H
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`define CONTROL_UNIT_H
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`include "instruction_classifier.sv"
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module control_unit (
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input logic [5:0] op, input logic [5:0] func,
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output logic [0:0] M2R, output logic [0:0] M2W,
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output logic [0:0] B,
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output logic [3:0] ALU_FN, output logic [0:0] ALU_SRC,
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output logic [0:0] RDST, output logic [0:0] RW
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);
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logic [0:0] TYPE_R;
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logic [0:0] TYPE_B1;
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logic [0:0] TYPE_J;
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logic [0:0] TYPE_B2;
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logic [0:0] TYPE_I;
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logic [0:0] TYPE_F;
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logic [0:0] TYPE_M;
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instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
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always_comb begin
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// TODO
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end
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endmodule;
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`endif |