Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

Merged incomming changes

modules/alu.sv

@@ -9,13 +9,25 @@
 // flags[1:1] = Overflow
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
-    output logic [2**width-1:0] OUT_1, output logic[1:0] flags,
+    output logic [2**width-1:0] OUT_1, output logic[1:0] flags
-	 output logic [7:0] out_seg1);
+`ifdef SYNTHESIS
+	, output logic [7:0] out_seg1);
+`else
+    );
+`endif
 
     logic [0:0] asu_op;
     logic [2**width-1:0] asu_out;
     logic [1:0] asu_flags;
+    logic [7:0] asu_seven_seg_out;
+
+    // NOTE: For demo only
+    // TODO: Strip this for assignment 2
+    `ifdef SYNTHESIS
+        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1], asu_seven_seg_out);
+    `else
         asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
+    `endif
 
     logic [2**width-1:0] lu_out;
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
@@ -35,6 +47,11 @@ module alu #(parameter width=2)(input logic [3:0] op,
             default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
         endcase
     end
-	 seven_seg dut(OUT_1, 1, out_seg1);
+
+    // NOTE: For demo only
+    // TODO: Strip this for assignment 2
+    `ifdef SYNTHESIS
+	    seven_seg dut(OUT_1, 1'b1, out_seg1);
+    `endif
 endmodule
 `endif

modules/asu.sv

@@ -5,8 +5,14 @@
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
-   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN,
+   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
-	output logic[7:0] out_seg_1);
+// Used to switch between demo mode and testbench mode
+// TODO: Strip for assignment 2
+`ifdef SYNTHESIS
+	, output logic[7:0] out_seg_1);
+`else
+    );
+`endif
 	
     logic [2**width-1:0] operand;
     always_comb begin
@@ -21,6 +27,10 @@ module asu #(parameter width = 2)(
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
 
-	 seven_seg dut(OUT_1, 1, out_seg_1);
+	// Include seven segment visual output for hardware builds only
+    // TODO: Strip this for assignment 2 outright
+    `ifdef SYNTHESIS 
+	    seven_seg dut(OUT_1, 1'b1, out_seg_1);
+    `endif
 endmodule
 `endif

tests/asu_tb.sv

@@ -1,6 +1,6 @@
 `include "asu.sv"
 
-module asu_tb #(width=8)();
+module asu_tb #(width=4)();
     logic [0:0] op;
     logic [width-1:0] A;
     logic [width-1:0] B;

tests/shifter_tb.sv

@@ -1,62 +1,62 @@
 `include "shifter.sv"
-module shifter_tb #(width=8)();
+module shifter_tb #(width=4)();
     logic [2:0] op;
-    logic [width-1:0] Y;
+    logic [2**width-1:0] Y;
-    logic [width-1:0] A_in;
+    logic [2**width-1:0] A_in;
-    logic [$clog2(width)-1:0] B_in;
+    logic [2**width-1:0] B_in;
     logic [width-1:0] C_in;
 
     logic [2:0] ops[6];
-    logic [width-1:0] A[6];
+    logic [2**width-1:0] A[6];
-    logic [$clog2(width)-1:0] B[6];
+    logic [2**width-1:0] B[6];
     logic [width-1:0] C[6];
-    logic [width-1:0] Y_exp[6];
+    logic [2**width-1:0] Y_exp[6];
 
-    shifter #(width) dut(op, A_in,C_in,B_in,Y);
+    shifter #(width) dut(op, A_in,B_in,C_in,Y);
 
     integer error_count;
     initial begin
         // Test left shift by C
         ops[0] = 3'b000;
-        A[0] = {{(width-1){1'b0}}, {1'b1}};
+        A[0] = {{(2**width-1){1'b0}}, {1'b1}};
         C[0] = {{(width-1){1'b0}}, {1'b1}};
-        B[0] = {width{1'b0}};
+        B[0] = {2**width{1'b0}};
-        Y_exp[0] = {{(width-2){1'b0}}, {2'b10}};
+        Y_exp[0] = {{(2**width-2){1'b0}}, {2'b10}};
 
         // Test left shift by B
         ops[1] = 3'b100;
-        A[1] = {{(width-1){1'b0}}, {1'b1}};
+        A[1] = {{(2**width-1){1'b0}}, {1'b1}};
         C[1] = {{(width-1){1'b0}}, {1'b1}};
-        B[1] = {{($clog2(width)-2){1'b0}}, 2'b10};
+        B[1] = {{(2**width-2){1'b0}}, 2'b10};
-        Y_exp[1] = {{(width-3){1'b0}}, {3'b100}};
+        Y_exp[1] = {{(2**width-3){1'b0}}, {3'b100}};
 
         // Test Logical right shift by C
         ops[2] = 3'b001;
-        A[2] = {{(width-2){1'b0}}, {2'b10}};
+        A[2] = {{(2**width-2){1'b0}}, {2'b10}};
         C[2] = {{(width-1){1'b0}}, {1'b1}};
-        B[2] = {width{1'b0}};
+        B[2] = {2**width{1'b0}};
-        Y_exp[2] = {{(width-1){1'b0}}, {1'b1}};
+        Y_exp[2] = {{(2**width-1){1'b0}}, {1'b1}};
 
         // Test Logical right shift by B
         ops[3] = 3'b101;
-        A[3] = {{(width-1){1'b0}}, {2'b10}};
+        A[3] = {{(2**width-1){1'b0}}, {2'b10}};
         C[3] = {{(width-1){1'b0}}, {1'b1}};
-        B[3] = {{($clog2(width)-2){1'b0}}, 2'b10};
+        B[3] = {{(2**width-2){1'b0}}, 2'b10};
-        Y_exp[3] = {{(width-1){1'b0}}, {1'b0}};
+        Y_exp[3] = {{(2**width-1){1'b0}}, {1'b0}};
 
         // Test arithmetic shift right by C
         ops[4] = 3'b011;
-        A[4] = {{(width-1){1'b1}}, 1'b0};   // -2
+        A[4] = {{(2**width-1){1'b1}}, 1'b0};   // -2
         C[4] = {{(width-1){1'b0}}, 1'b1};   // 1
-        B[4] = {{(width-2){1'b0}}, 2'b10};  // 2
+        B[4] = {{(2**width-2){1'b0}}, 2'b10};  // 2
-        Y_exp[4] = {width{1'b1}};           // -1
+        Y_exp[4] = {2**width{1'b1}};           // -1
 
         // Test arithmetic shift right by B
         ops[5] = 3'b111;
-        A[5] = {{(width-2){1'b1}}, 2'b00};   // -4
+        A[5] = {{(2**width-2){1'b1}}, 2'b00};   // -4
         C[5] = {{(width-1){1'b0}}, 1'b1};   // 1
-        B[5] = {{(width-2){1'b0}}, 2'b10};  // 2
+        B[5] = {{(2**width-2){1'b0}}, 2'b10};  // 2
-        Y_exp[5] = {width{1'b1}};           // -1
+        Y_exp[5] = {2**width{1'b1}};           // -1
 
         error_count = 0;
         $display("Beginning Shifter tests");