Added zero initialization for r0

modules/ram.sv

@@ -1,4 +1,4 @@
-module RAM #(addrwidth=9, datawidth=5)(
+module rom #(addrwidth=9, datawidth=5)(
     input logic [0:0] clk,
     input logic [2**addrwidth-1:0] addr,
     input logic [0:0] we,

modules/register_file.sv

@@ -10,6 +10,10 @@ module register_file #(parameter width=5, parameter nregs=32)(
     localparam BW = 2**width;
     logic [2**width-1:0] regs[nregs];
 
+    initial begin
+        regs[0] = {(2**width){1'b0}};
+    end
+
     always_ff @(posedge clk) begin
         if (we & (WA != {(2**width){1'b0}} )) begin
             regs[WA] <= WD;

modules/rom.sv

@@ -1,5 +1,5 @@
 
-module ROM #(parameter m=7,p=4) (
+module rom #(parameter m=7,p=4) (
         input logic [m-1:0] Ad,
         output logic [p-1:0] Dout
     );
@@ -16,4 +16,4 @@ module ROM #(parameter m=7,p=4) (
             $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
         `endif
     end
-endmodule // end ROM module
+endmodule // end rom module