Updated assignment2. Created file for testing R-type instructions, still needs to be implemented. Consider using bind to be able to extract inner-scoped variables out for inspection.

modules/alu.sv

@@ -8,12 +8,12 @@
 // flags[1:1] = Overflow
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
-    output logic [2**width-1:0] OUT_1, output logic[1:0] flags
+    output logic [2**width-1:0] OUT_1, output logic[2:0] flags
     );
     // intermediate logic for handling asu output
     logic [0:0] asu_op;
     logic [2**width-1:0] asu_out;
-    logic [1:0] asu_flags;
+    logic [2:0] asu_flags;
 
     asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
 
@@ -21,6 +21,7 @@ module alu #(parameter width=2)(input logic [3:0] op,
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
 
     always_comb begin
+        asu_flags[2] = (A == B);
         case (op) 
             4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
             4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end

modules/assignment2.sv

@@ -9,11 +9,14 @@
 `include "instruction_module_classifier.sv"
 `include "alu.sv"
 `include "shifter.sv"
+`include "sign_extender.sv"
 `include "seven_seg_4digit.sv"
 
 
 module assignment2 #(width=5, ramsz=9, romsz=10) (
-	input logic [0:0] clk,
+	input logic [0:0] clk
+`ifdef SYNTHESIS
+    ,
 	input logic [4:0] HID_Register,
 	input logic [0:0] HID_PC,
 	input logic [0:0] HID_Hi_Low,
@@ -22,6 +25,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	output logic[7:0] out_seg_1,
 	output logic[7:0] out_seg_2,
 	output logic[7:0] out_seg_3
+`endif
 	);
 	// Intermediate for displaying high / low of PC or Register
 	logic[15:0] PC_Reg_Display;
@@ -48,7 +52,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [0:0] en_alu;
 	
 	// Register File intermediates
-	logic [1:0] flags;
+	logic [2:0] flags;
 	logic [2**width-1:0] rs;
 	logic [2**width-1:0] rt;
 	logic [2**width-1:0] rd;
@@ -72,6 +76,12 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 		rs, instruction[25:21],
 		rt, instruction[20:16]
    );
+    // Always use sign-extension
+    logic [2**width-1:0] rt_imm;
+    sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
+    // TODO:
+    //  - ALU srcB
+    //  - PCBranch (rel jump of 4-byte words)
 
 	logic [2**width-1:0] rd_alu;
 	alu #(width) ALU (instruction[3:0], rs, rt, rd_alu, flags[1:0]);
@@ -79,7 +89,13 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] rd_shifter;
 	shifter #(width) SHIFTER (instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
     
-	assign rd = en_alu ? rd_alu : (en_shifter ? rd_shifter : {2**width{1'b0}});
+
+	assign rd = (I | (R & en_alu)) ? rd_alu : ( (R & en_shifter) ? rd_shifter : {2**width{1'b1}});
+	assign rd_we = M; // TODO: Verify if diagram is in order
+
+
+
+
 
 	// Temporary Test output
 	assign PC_Reg_Display = 16'hC342;

modules/sign_extender.sv

@@ -0,0 +1,13 @@
+`ifndef SIGN_EXTENDER_H
+`define SIGN_EXTENDER_H
+
+module sign_extender #(in_width=4, out_width=5)(
+    input logic [0:0] op,
+    input logic [2**in_width-1:0] val,
+    output logic [2**out_width-1:0] ext_val
+);
+    always_comb begin
+        assign ext_val = (op) ? {{(2**(out_width-in_width)){val[2**in_width-1]}}, val} : ({{(2**(out_width-in_width)){1'b0}}, val});
+    end
+endmodule
+`endif

tests/alu_tb.sv

@@ -16,14 +16,14 @@ module alu_tb #(width=2)();
     logic [2**width-1:0] A_in;
     logic [2**width-1:0] B_in;
     logic [2**width-1:0] Y_out;
-    logic [1:0] flags_out;
+    logic [2:0] flags_out;
 
     localparam int NUM_TESTS = 28;
     logic [3:0] ops[NUM_TESTS];
     logic [2**width-1:0] A_cases[NUM_TESTS];
     logic [2**width-1:0] B_cases[NUM_TESTS];
     logic [2**width-1:0] Y_exp[NUM_TESTS];
-    logic [1:0] flags_exp[NUM_TESTS];
+    logic [2:0] flags_exp[NUM_TESTS];
 
     alu #(width) dut (op_in, A_in, B_in, Y_out, flags_out);
 

tests/mips-rtype.sv

@@ -0,0 +1,6 @@
+`include "assignment2.sv"
+
+
+module mips_rtype_tb(input logic [0:0] clk);
+    assignment2 #(5) CPU (clk);
+endmodule