Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/register_file.sv

@@ -6,6 +6,7 @@ module register_file #(parameter width=5, parameter nregs=5)(
     input logic [nregs-1:0] WA, input logic [2**width-1:0] WD,
     input logic [nregs-1:0] RA1, output logic [2**width-1:0] RD1,
     input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2
+    output logic [2**width-1:0] regs_out [2**nregs]
 );
     localparam BW = 2**width;
     logic [2**width-1:0] regs[2**nregs];
@@ -22,5 +23,6 @@ module register_file #(parameter width=5, parameter nregs=5)(
 
     assign RD1 = regs[RA1];
     assign RD2 = regs[RA2];
+    assign regs_out = regs;  // Expose registers externally
 endmodule
 `endif