TroubleElectrical/FPGA_Uni
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f91fe0681ab6b61ee295a1d5304641626a47b593
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6 Commits
Author SHA1 Message Date
riley f91fe0681a Fixed parameter ordering in instancing 2026-10-13 12:45:15 +11:00
riley ba9ab863d8 Fixed ordering for instruction counter and added module output gating for writing 2026-10-13 12:33:24 +11:00
riley 6d731b5a6b Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-13 12:29:52 +11:00
riley b9623569cf Partially implemented R-type instructions (still need to write rd values) 2026-10-13 12:26:26 +11:00
TroubleElectrical e57e8f362a Updated assignment 2 dependency modules (currently 8 errors in compile) 2026-10-13 12:23:52 +11:00
riley dacc49efac TODO 2026-10-08 15:58:06 +11:00