5 Commits

Include renames

Author	SHA1	Message	Date
riley	75ef513efa	Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag	2026-10-13 21:34:25 +11:00
riley	78efccfe1e	Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output	2026-09-13 23:08:07 +10:00
riley	f69f87ccab	Just add cases for ALU testbench. The structure of the ALU testbench is now implemented.	2026-09-10 15:57:56 +10:00
riley	a89a66d34d	Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage	2026-09-03 16:32:56 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00