4 Commits

Include renames

Author	SHA1	Message	Date
riley	ef6bd3aec9	Added test assemblies for assignment 3 / pipelining	2026-11-04 15:42:22 +11:00
riley	973b9260b6	Fixed (maybe bug) in demo program where program branches back to prior instruction.	2026-10-20 16:21:55 +11:00
riley	4c7e2ff085	Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues.	2026-10-16 11:29:04 +11:00
riley	76cd7931b6	Realized that, while the assembled is not binary, it is still loadable by verilog.	2026-10-08 14:18:11 +11:00