3 Commits

Include renames

Author	SHA1	Message	Date
riley	f5a2455849	Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason.	2026-09-08 21:31:18 +10:00
riley	00d9e3de88	Fixed error where assignment was not within a combinational/sequential block	2026-09-08 18:23:27 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00