This website requires JavaScript.
Explore
Help
Sign In
TroubleElectrical
/
FPGA_Uni
Watch
1
Star
0
Fork
0
Code
Issues
1
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
24
Commits
2
Branches
0
Tags
e9feb3cb8d99eb8dbc69302bf19d0b73de0c1f36
Commit Graph
2 Commits
Include renames
Author
SHA1
Message
Date
TroubleElectrical
a73990b242
Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
2026-09-10 15:24:44 +10:00
TroubleElectrical
dc32347c9b
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00