TroubleElectrical/FPGA_Uni
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e7fff9f3dce83d8844e80ec4f9cf2b8ea12bd8ab
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24 Commits
Author SHA1 Message Date
riley e7fff9f3dc Added explicit rst input to RAM and PC as well as the MIPS processor. 2026-10-16 12:11:19 +11:00
riley 5ae9125e06 Fixed a couple bugs introduced from merge-conflict resolution 2026-10-16 11:50:07 +11:00
riley 8a682347f0 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-16 11:44:03 +11:00
riley 92a0cb17da Updated assignment 2 to reflect prior changes. Fixed instruction ordering for register file module (again). Fixed typo that limited the space the ALU could write its flags out to. Swapped ordering to be correct when determining if we are storing the result from ALU or MEM. 
Added a QUARTUS_SYNTH around the display logic at the end of the module.
Partially fixed control_unit module, still seems to need some changes as branching doesn't appear to work at all.
 2026-10-16 11:38:35 +11:00
TroubleElectrical 5d9e7f541e Updated RAM code to make sure Bus width is 32 bits 2026-10-16 11:32:47 +11:00
riley 04d1d3e2fe Added control unit. TODO: Test 2026-10-15 15:53:59 +11:00
riley 2e042fbd93 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 15:18:09 +11:00
riley a336df9d80 Reworked CPU to use control unit 2026-10-15 15:16:57 +11:00
TroubleElectrical afb6fefe1b Updated Assignment2 with better register file module insantiation 2026-10-15 15:07:41 +11:00
TroubleElectrical 10bf499065 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 14:52:14 +11:00
TroubleElectrical 8c6765eb83 Updated reg file and assignment for compilation 2026-10-15 14:49:32 +11:00
riley 1c93c082ae Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 14:48:06 +11:00
riley d9f44f93df Halfway added imm,branch and mem ops 2026-10-15 14:46:51 +11:00
TroubleElectrical ac1062fbd5 Added Register Display Code 2026-10-15 14:35:10 +11:00
riley 1e13de9301 Updated assignment2. Created file for testing R-type instructions, still needs to be implemented. Consider using bind to be able to extract inner-scoped variables out for inspection. 2026-10-13 22:26:52 +11:00
TroubleElectrical 25a953cdc6 Added 4 digit 7seg display module (confirmed working for now), 
Added Inputs for displaying registers / Program Counter high and low bits,
Assigned pins for Display digits, inputs (Labeled HID) and the clk button
 2026-10-13 16:32:15 +11:00
TroubleElectrical 353923eadf Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes) 2026-10-13 15:12:00 +11:00
TroubleElectrical 19b07b649d Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments) 2026-10-13 13:24:44 +11:00
riley f91fe0681a Fixed parameter ordering in instancing 2026-10-13 12:45:15 +11:00
riley ba9ab863d8 Fixed ordering for instruction counter and added module output gating for writing 2026-10-13 12:33:24 +11:00
riley 6d731b5a6b Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-13 12:29:52 +11:00
riley b9623569cf Partially implemented R-type instructions (still need to write rd values) 2026-10-13 12:26:26 +11:00
TroubleElectrical e57e8f362a Updated assignment 2 dependency modules (currently 8 errors in compile) 2026-10-13 12:23:52 +11:00
riley dacc49efac TODO 2026-10-08 15:58:06 +11:00