4 Commits

Include renames

Author	SHA1	Message	Date
TroubleElectrical	5d9e7f541e	Updated RAM code to make sure Bus width is 32 bits	2026-10-16 11:32:47 +11:00
TroubleElectrical	afb6fefe1b	Updated Assignment2 with better register file module insantiation	2026-10-15 15:07:41 +11:00
TroubleElectrical	8c6765eb83	Updated reg file and assignment for compilation	2026-10-15 14:49:32 +11:00
TroubleElectrical	353923eadf	Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)	2026-10-13 15:12:00 +11:00