3 Commits

Include renames

Author	SHA1	Message	Date
TroubleElectrical	5d9e7f541e	Updated RAM code to make sure Bus width is 32 bits	2026-10-16 11:32:47 +11:00
TroubleElectrical	8c6765eb83	Updated reg file and assignment for compilation	2026-10-15 14:49:32 +11:00
TroubleElectrical	ac1062fbd5	Added Register Display Code	2026-10-15 14:35:10 +11:00