6 Commits

Include renames

Author	SHA1	Message	Date
riley	49f539c855	Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND)	2026-09-13 23:35:05 +10:00
riley	19ba1bf473	Added header guards to prevent errors from double-inclusions	2026-09-13 23:09:08 +10:00
riley	cd7074a78c	Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es	2026-09-10 15:56:59 +10:00
riley	f5a2455849	Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason.	2026-09-08 21:31:18 +10:00
riley	00d9e3de88	Fixed error where assignment was not within a combinational/sequential block	2026-09-08 18:23:27 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00