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Author	SHA1	Message	Date
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00
riley	0c21734447	Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented	2026-09-03 15:25:07 +10:00
TroubleElectrical	41252763d4	Test commit	2026-09-03 15:12:25 +10:00
TroubleElectrical	28bfe10398	Initial commit	2026-09-03 15:04:27 +10:00