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FPGA_Uni
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TroubleElectrical
9e5fb6f52b
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
TroubleElectrical
2208eb4f16
Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.
2026-09-08 15:36:51 +10:00