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TroubleElectrical
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FPGA_Uni
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9e5fb6f52b50bb1d56b14554611f4ffa5ed384a0
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3 Commits
Include renames
Author
SHA1
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Date
TroubleElectrical
9e5fb6f52b
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
TroubleElectrical
3114cd6b80
Added the updated A1_Q1 Quartus compilation
2026-09-03 19:22:52 +10:00
TroubleElectrical
31a4496904
Including quartus prime lite edition project folders for flashing the project to the board
2026-09-03 16:34:31 +10:00