5 Commits

Include renames

Author	SHA1	Message	Date
riley	2f3ecb9a3c	Updated instruction counter to have an enable/disable port	2026-11-11 15:24:41 +11:00
riley	e7fff9f3dc	Added explicit rst input to RAM and PC as well as the MIPS processor.	2026-10-16 12:11:19 +11:00
riley	0ea3e0fa12	Added initialisation blocks for PC and GPR's	2026-10-16 11:33:45 +11:00
TroubleElectrical	e57e8f362a	Updated assignment 2 dependency modules (currently 8 errors in compile)	2026-10-13 12:23:52 +11:00
riley	0ef2aeeb48	Added instruction counter and register file	2026-10-08 14:13:38 +11:00