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TroubleElectrical/FPGA_Uni
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Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
59 Commits 2 Branches 0 Tags
76cd7931b64c9939e7581dd18cfc0f6fd63e3da2
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4 Commits
Author SHA1 Message Date
TroubleElectrical 9e5fb6f52b Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board 2026-09-15 16:52:48 +10:00
TroubleElectrical 05361dcf70 Added all Testbenches to Modelsim and confirmed working operation 2026-09-15 15:15:00 +10:00
TroubleElectrical a73990b242 Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2) 2026-09-10 15:24:44 +10:00
TroubleElectrical dc32347c9b Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3) 2026-09-09 14:27:11 +10:00
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