12 Commits

Include renames

Author	SHA1	Message	Date
riley	a647305bd9	Fixed bug where ram datawidth was not 2^N.	2026-10-20 16:01:34 +11:00
riley	e7fff9f3dc	Added explicit rst input to RAM and PC as well as the MIPS processor.	2026-10-16 12:11:19 +11:00
riley	5ae9125e06	Fixed a couple bugs introduced from merge-conflict resolution	2026-10-16 11:50:07 +11:00
riley	8a682347f0	Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni	2026-10-16 11:44:03 +11:00
riley	878f949e5f	Made addrwidth sizing consistent with the 2^N used everywhere	2026-10-16 11:34:31 +11:00
TroubleElectrical	5d9e7f541e	Updated RAM code to make sure Bus width is 32 bits	2026-10-16 11:32:47 +11:00
TroubleElectrical	cdde70e6c2	Updated ram.sv to resolve compilation error	2026-10-15 15:42:26 +11:00
riley	5fc24f7859	Temp change to make RAM word-aligned	2026-10-15 15:28:27 +11:00
TroubleElectrical	e57e8f362a	Updated assignment 2 dependency modules (currently 8 errors in compile)	2026-10-13 12:23:52 +11:00
riley	1faa7fc3f0	Updated ram and rom modules so that naming is more consistent	2026-10-12 11:49:35 +11:00
riley	102d5b4b7a	Updated RAM interface to be more inline with ROM interface	2026-10-08 14:56:52 +11:00
riley	ab561dd510	Implemented RAM. Possible issue by using async assignments in initial begin.	2026-10-08 14:55:28 +11:00