2 Commits

Include renames

Author	SHA1	Message	Date
riley	8f9ec010ac	Updated gate register module to support arbitary delays to prevent littering uper-level code with gatereg->gatereg logic values.	2026-11-04 15:40:25 +11:00
riley	b046ad7db0	Created register for gating pipeline stage results	2026-10-29 15:34:31 +11:00