9 Commits

Include renames

Author	SHA1	Message	Date
riley	6b938a24be	Updated tests.sv to not perform prior module tests. Seperated testbenches for hazard and nohazard tests.	2026-11-12 12:33:24 +11:00
riley	38fa35fccd	Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module	2026-11-05 14:10:13 +11:00
riley	704286f0e6	Renamed MIPS test to be a single cycle test	2026-11-04 15:42:52 +11:00
riley	103aa769fd	Added testbench for MIPS processor	2026-10-16 03:54:55 +11:00
riley	78efccfe1e	Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output	2026-09-13 23:08:07 +10:00
riley	42f4e661dc	Implemented shifter and its test bench code fully	2026-09-08 22:35:14 +10:00
riley	f5a2455849	Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason.	2026-09-08 21:31:18 +10:00
riley	a89a66d34d	Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage	2026-09-03 16:32:56 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00