13 Commits

Include renames

Author	SHA1	Message	Date
riley	12ae58ad86	Removed flag assignment from within ALU OP case statement and instead perform it at the end. Made bit index for the ASU OP more explicit.	2026-10-16 11:32:24 +11:00
riley	d9f44f93df	Halfway added imm,branch and mem ops	2026-10-15 14:46:51 +11:00
riley	75ef513efa	Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag	2026-10-13 21:34:25 +11:00
TroubleElectrical	179eb469c4	Removed seven segment code from alu and asu	2026-09-24 15:37:48 +10:00
TroubleElectrical	13f34e62c6	Added Q4 sumbission and comments	2026-09-16 12:50:58 +10:00
riley	19cd7ac177	Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2.	2026-09-15 21:27:04 +10:00
TroubleElectrical	9d0c7011ce	Updated ALU (Q4) with 7seg and confirmed operation on board	2026-09-15 19:05:04 +10:00
riley	4df723318b	Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis	2026-09-13 23:53:47 +10:00
riley	78efccfe1e	Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output	2026-09-13 23:08:07 +10:00
riley	37644c629e	Fixed bug of confuddling width with 2^n and w.	2026-09-10 15:42:50 +10:00
riley	669357ccc0	Implemented ALU. Still needs testbench and testing done.	2026-09-10 15:38:36 +10:00
TroubleElectrical	dc32347c9b	Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)	2026-09-09 14:27:11 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00