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TroubleElectrical/FPGA_Uni
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Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
105 Commits 2 Branches 0 Tags
65be2c2d6169bc507ad9422a8bc3d4eb1535cb3c
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3 Commits
Author SHA1 Message Date
riley 4c7e2ff085 Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues. 2026-10-16 11:29:04 +11:00
riley 76cd7931b6 Realized that, while the assembled is not binary, it is still loadable by verilog. 2026-10-08 14:18:11 +11:00
riley aab18425f9 Added test assembly code 2026-10-08 14:08:35 +11:00
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