5 Commits

Include renames

Author	SHA1	Message	Date
riley	b52f01c3be	Added some delay to better test final branch/halt.	2026-10-20 16:02:40 +11:00
riley	2f652705cc	Fixed timing in testbench for branch iteration.	2026-10-16 12:51:21 +11:00
riley	e7fff9f3dc	Added explicit rst input to RAM and PC as well as the MIPS processor.	2026-10-16 12:11:19 +11:00
riley	559ff01d69	Fixed printing annoyance. Added variable dumping to a wavefile. Updated delay to 2 units (as there is 1 unit of clk being high and 1 unit low). ... Removed register initialisation code from testbench. Fixed typo when wanting to check T0 (R8) but was checking R0. Added explicit if-else begin-end blocks to logging and a simulation exit when the testbench is done.	2026-10-16 11:41:33 +11:00
riley	19e5843d55	Added testbench for MIPS processor	2026-10-16 03:53:14 +11:00