TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
7 Commits 2 Branches 0 Tags
31a4496904fd4610457c5e44df8de66e42ae47d3
Commit Graph
1 Commits
Author SHA1 Message Date
riley 6668969b03 Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v 2026-09-03 16:05:52 +10:00