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TroubleElectrical/FPGA_Uni
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Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
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25ed477df9a31780cbbf24627e472c3a3491f7f7
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4 Commits
Author SHA1 Message Date
riley 3af4bfc875 Added attribution to submission files 2026-09-16 13:35:35 +10:00
TroubleElectrical 64cd876f12 Added attribution for submission files 2026-09-16 13:01:43 +10:00
TroubleElectrical 56ade6b426 Added comments to Logic Unit (Q2) and added to submission file 2026-09-16 12:38:06 +10:00
riley 900b544bc6 Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
Renamed submission folder to fix typo.
2026-09-15 22:00:02 +10:00
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