5 Commits

Include renames

Author	SHA1	Message	Date
TroubleElectrical	56ade6b426	Added comments to Logic Unit (Q2) and added to submission file	2026-09-16 12:38:06 +10:00
riley	4df723318b	Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis	2026-09-13 23:53:47 +10:00
riley	19ba1bf473	Added header guards to prevent errors from double-inclusions	2026-09-13 23:09:08 +10:00
TroubleElectrical	2208eb4f16	Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.	2026-09-08 15:36:51 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00