 riley
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287fc1903d
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Updated default ASU testbench width to be 4-bit to align with seven segment width for demo
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2026-09-15 21:28:01 +10:00 |
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riley
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5acf1c8b87
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Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable
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2026-09-08 22:49:22 +10:00 |
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riley
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a89a66d34d
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Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
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2026-09-03 16:32:56 +10:00 |
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riley
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6668969b03
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Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v
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2026-09-03 16:05:52 +10:00 |
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