4 Commits

Include renames

Author	SHA1	Message	Date
TroubleElectrical	b49e294b7d	Updated register_file.sv with proper naming scheme and 32bit width	2026-10-08 15:10:40 +11:00
TroubleElectrical	c27a04ef73	Implemented instruction classifier on board (Q6) and added blank submission files (for now)	2026-09-15 20:00:35 +10:00
TroubleElectrical	05361dcf70	Added all Testbenches to Modelsim and confirmed working operation	2026-09-15 15:15:00 +10:00
TroubleElectrical	32eea036a8	Added projects for A1 q2 to q6	2026-09-04 13:12:33 +10:00