6 Commits

Include renames

Author	SHA1	Message	Date
TroubleElectrical	ae8ac98e8d	Added Q5 comments and sumbission	2026-09-16 12:54:18 +10:00
TroubleElectrical	9583abd307	Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)	2026-09-15 19:43:28 +10:00
riley	4df723318b	Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis	2026-09-13 23:53:47 +10:00
riley	19ba1bf473	Added header guards to prevent errors from double-inclusions	2026-09-13 23:09:08 +10:00
riley	42f4e661dc	Implemented shifter and its test bench code fully	2026-09-08 22:35:14 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00