Fixed bug in test code where there was a hazzard, despite testing assuming no hazzard. Updated testbench to reflect this (Ln57-62).

Added mem[0x000] to log message when printing registers.
Replaced 8 delay with explicit 5x 2 delays. (NOTE: Needed an extra one for ensuring write-back when comparing results.
Fixed bug where the wrong registers were being added together when creating the comparison point in the testbench.
Fixed testbench bug where S4 was checked twice and S5 not checked at all.
Updated display message on test failure to reflect that it is the pipelined version, not the single-cycle.

asm/src/ELEC4720-2026s2-Ass-03-NoHazardsDemo.s

@@ -26,6 +26,9 @@ main:
 	subu $t2, $t2, $t2 # Set t2 = 0 
 	subu $t3, $t3, $t3 # Set t3 = 0 
 	addiu $t1, $t0, 7  # Set t1 = 7 (R9)
+	subu $t3, $t3, $t3 # Set t3 = 0 
+	subu $t3, $t3, $t3 # Set t3 = 0 
+	subu $t3, $t3, $t3 # Set t3 = 0 
 
 	# Memory operations
 	sw $t1, 0x10000000($t0) # Save t1 to memory (change to 0x0000 for FPGA)