Updated assignment 2 dependency modules (currently 8 errors in compile)

modules/ram.sv

@@ -1,4 +1,7 @@
-module rom #(addrwidth=9, datawidth=5)(
+`ifndef RAM_H
+`define RAM_H
+
+module ram #(addrwidth=9, datawidth=5)(
     input logic [0:0] clk,
     input logic [2**addrwidth-1:0] addr,
     input logic [0:0] we,
@@ -15,11 +18,13 @@ module rom #(addrwidth=9, datawidth=5)(
         end
     end
 
-    always_ff(@posedge clk) begin
+    always_ff @(posedge clk) begin
         if (we) begin
             mem[addr] <= data_in;
         end
     end
     assign data_out = mem[addr];
 
-endmodule;
+endmodule
+
+`endif