diff --git a/Quartus/A2/assignment2.qsf b/Quartus/A2/assignment2.qsf index 90ea31b..d08adfc 100644 --- a/Quartus/A2/assignment2.qsf +++ b/Quartus/A2/assignment2.qsf @@ -54,4 +54,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/A2/db/assignment2.cmp.rdb b/Quartus/A2/db/assignment2.cmp.rdb new file mode 100644 index 0000000..3d32a8e Binary files /dev/null and b/Quartus/A2/db/assignment2.cmp.rdb differ diff --git a/Quartus/A2/db/assignment2.map.qmsg b/Quartus/A2/db/assignment2.map.qmsg new file mode 100644 index 0000000..b754c22 --- /dev/null +++ b/Quartus/A2/db/assignment2.map.qmsg @@ -0,0 +1,15 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791854502822 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791854502823 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 12:21:42 2026 " "Processing started: Tue Oct 13 12:21:42 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791854502823 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854502823 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854502823 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791854503126 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791854503126 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_we assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_we\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_addr assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_addr\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \")\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(27) " "Verilog HDL syntax error at assignment2.sv(27) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 27 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(28) " "Verilog HDL syntax error at assignment2.sv(28) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(29) " "Verilog HDL syntax error at assignment2.sv(29) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 29 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(20) " "Ignored design unit \"assignment2\" at assignment2.sv(20) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 20 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854512634 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 8 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 12:21:52 2026 " "Processing ended: Tue Oct 13 12:21:52 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854512678 ""} diff --git a/Quartus/A2/db/assignment2.map.rdb b/Quartus/A2/db/assignment2.map.rdb new file mode 100644 index 0000000..676973d Binary files /dev/null and b/Quartus/A2/db/assignment2.map.rdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.hdb b/Quartus/A2/db/assignment2.map_bb.hdb new file mode 100644 index 0000000..24f33df Binary files /dev/null and b/Quartus/A2/db/assignment2.map_bb.hdb differ diff --git a/Quartus/A2/db/assignment2.sld_design_entry.sci b/Quartus/A2/db/assignment2.sld_design_entry.sci new file mode 100644 index 0000000..7a5b911 Binary files /dev/null and b/Quartus/A2/db/assignment2.sld_design_entry.sci differ diff --git a/Quartus/A2/db/assignment2.smart_action.txt b/Quartus/A2/db/assignment2.smart_action.txt new file mode 100644 index 0000000..11b531f --- /dev/null +++ b/Quartus/A2/db/assignment2.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/Quartus/A2/db/assignment2.tis_db_list.ddb b/Quartus/A2/db/assignment2.tis_db_list.ddb new file mode 100644 index 0000000..781db1e Binary files /dev/null and b/Quartus/A2/db/assignment2.tis_db_list.ddb differ diff --git a/Quartus/A2/db/prev_cmp_assignment2.qmsg b/Quartus/A2/db/prev_cmp_assignment2.qmsg new file mode 100644 index 0000000..ffbf67b --- /dev/null +++ b/Quartus/A2/db/prev_cmp_assignment2.qmsg @@ -0,0 +1,22 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791854431570 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791854431571 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 12:20:31 2026 " "Processing started: Tue Oct 13 12:20:31 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791854431571 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854431571 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854431571 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791854431890 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791854431890 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"end\"; \"end\" without \"begin\" instruction_counter.sv(18) " "Verilog HDL syntax error at instruction_counter.sv(18) near text: \"end\"; \"end\" without \"begin\" . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 18 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440693 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "instruction_counter instruction_counter.sv(4) " "Ignored design unit \"instruction_counter\" at instruction_counter.sv(4) due to previous errors" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440694 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "instruction_classifier instruction_classifier.sv(3) " "Ignored design unit \"instruction_classifier\" at instruction_classifier.sv(3) due to previous errors" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440694 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "asu asu.sv(4) " "Ignored design unit \"asu\" at asu.sv(4) due to previous errors" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440695 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "lu lu.sv(3) " "Ignored design unit \"lu\" at lu.sv(3) due to previous errors" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440695 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "alu alu.sv(9) " "Ignored design unit \"alu\" at alu.sv(9) due to previous errors" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440695 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440695 ""} +{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_we assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_we\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} +{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_addr assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_addr\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \")\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(27) " "Verilog HDL syntax error at assignment2.sv(27) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 27 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(28) " "Verilog HDL syntax error at assignment2.sv(28) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(29) " "Verilog HDL syntax error at assignment2.sv(29) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 29 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(20) " "Ignored design unit \"assignment2\" at assignment2.sv(20) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 20 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854440697 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 14 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 14 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791854440753 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 12:20:40 2026 " "Processing ended: Tue Oct 13 12:20:40 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791854440753 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791854440753 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791854440753 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854440753 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 16 s 1 " "Quartus Prime Full Compilation was unsuccessful. 16 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854441416 ""} diff --git a/Quartus/A2/output_files/assignment2.flow.rpt b/Quartus/A2/output_files/assignment2.flow.rpt new file mode 100644 index 0000000..f8a77d2 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.flow.rpt @@ -0,0 +1,119 @@ +Flow report for assignment2 +Tue Oct 13 12:21:52 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-------------------------------------------------------------------------------+ +; Flow Summary ; ++-----------------------------+-------------------------------------------------+ +; Flow Status ; Flow Failed - Tue Oct 13 12:21:52 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; N/A until Partition Merge ; +; Total registers ; N/A until Partition Merge ; +; Total pins ; N/A until Partition Merge ; +; Total virtual pins ; N/A until Partition Merge ; +; Total block memory bits ; N/A until Partition Merge ; +; Total PLLs ; N/A until Partition Merge ; +; Total DLLs ; N/A until Partition Merge ; ++-----------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 10/13/2026 12:21:43 ; +; Main task ; Compilation ; +; Revision Name ; assignment2 ; ++-------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +; COMPILER_SIGNATURE_ID ; 268883478169649.179185450204071 ; -- ; -- ; -- ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ; +; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; ; -- ; -- ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 400 MB ; 00:00:25 ; +; Total ; 00:00:10 ; -- ; -- ; 00:00:25 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+---------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+---------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; ++----------------------+---------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 + + + diff --git a/Quartus/A2/output_files/assignment2.map.rpt b/Quartus/A2/output_files/assignment2.map.rpt new file mode 100644 index 0000000..180c01b --- /dev/null +++ b/Quartus/A2/output_files/assignment2.map.rpt @@ -0,0 +1,183 @@ +Analysis & Synthesis report for assignment2 +Tue Oct 13 12:21:52 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Failed - Tue Oct 13 12:21:52 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A until Partition Merge ; +; Total registers ; N/A until Partition Merge ; +; Total pins ; N/A until Partition Merge ; +; Total virtual pins ; N/A until Partition Merge ; +; Total block memory bits ; N/A until Partition Merge ; +; Total PLLs ; N/A until Partition Merge ; +; Total DLLs ; N/A until Partition Merge ; ++-----------------------------+-------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 5CGXFC5C6F27C7 ; ; +; Top-level entity name ; assignment2 ; assignment2 ; +; Family name ; Cyclone V ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 3 ; 3 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Automatic Parallel Synthesis ; On ; On ; +; Partial Reconfiguration Bitstream ID ; Off ; Off ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Oct 13 12:21:42 2026 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Error (10170): Verilog HDL syntax error at assignment2.sv(26) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 +Error (10149): Verilog HDL Declaration error at assignment2.sv(26): identifier "pc_we" is already declared in the present scope File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 +Error (10149): Verilog HDL Declaration error at assignment2.sv(26): identifier "pc_addr" is already declared in the present scope File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 +Error (10170): Verilog HDL syntax error at assignment2.sv(26) near text: ")"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 +Error (10170): Verilog HDL syntax error at assignment2.sv(27) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 27 +Error (10170): Verilog HDL syntax error at assignment2.sv(28) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 +Error (10170): Verilog HDL syntax error at assignment2.sv(29) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 29 +Error (10112): Ignored design unit "assignment2" at assignment2.sv(20) due to previous errors File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 20 +Info (12021): Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv +Error: Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 1 warning + Error: Peak virtual memory: 400 megabytes + Error: Processing ended: Tue Oct 13 12:21:52 2026 + Error: Elapsed time: 00:00:10 + Error: Total CPU time (on all processors): 00:00:25 + + diff --git a/Quartus/A2/output_files/assignment2.map.summary b/Quartus/A2/output_files/assignment2.map.summary new file mode 100644 index 0000000..473bad4 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.map.summary @@ -0,0 +1,12 @@ +Analysis & Synthesis Status : Failed - Tue Oct 13 12:21:52 2026 +Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Revision Name : assignment2 +Top-level Entity Name : assignment2 +Family : Cyclone V +Logic utilization (in ALMs) : N/A until Partition Merge +Total registers : N/A until Partition Merge +Total pins : N/A until Partition Merge +Total virtual pins : N/A until Partition Merge +Total block memory bits : N/A until Partition Merge +Total PLLs : N/A until Partition Merge +Total DLLs : N/A until Partition Merge diff --git a/modules/assignment2.sv b/modules/assignment2.sv index ed1d9f7..f934ee3 100644 --- a/modules/assignment2.sv +++ b/modules/assignment2.sv @@ -1,8 +1,20 @@ -`include "rom.sv" -`include "ram.sv" -`include "instruction_counter.sv" -`include "instruction_classifier.sv" -`include "alu.sv" +`ifndef ASS_2_SV +`define ASS_2_SV + +`ifdef SYNTHESIS + `include "../../rom.sv" + `include "../../ram.sv" + `include "../../instruction_counter.sv" + `include "../../instruction_classifier.sv" + `include "../../alu.sv" +`else + `include "rom.sv" + `include "ram.sv" + `include "instruction_counter.sv" + `include "instruction_classifier.sv" + `include "alu.sv" +`endif + module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk); @@ -16,4 +28,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk); RAM ram #(ramsz, 2**width)(); alu alu #(width)(); -endmodule \ No newline at end of file +endmodule + +`endif \ No newline at end of file diff --git a/modules/assignment2.sv.bak b/modules/assignment2.sv.bak new file mode 100644 index 0000000..ed1d9f7 --- /dev/null +++ b/modules/assignment2.sv.bak @@ -0,0 +1,19 @@ +`include "rom.sv" +`include "ram.sv" +`include "instruction_counter.sv" +`include "instruction_classifier.sv" +`include "alu.sv" + + +module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk); + + logic [romsz-1:0] pc_addr; + logic [0:0] pc_we; + logic [2**width-1:0] instruction; + + instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr); + ROM rom #(romsz, 2**width)(); + RAM ram #(ramsz, 2**width)(); + alu alu #(width)(); + +endmodule \ No newline at end of file diff --git a/modules/instruction_counter.sv b/modules/instruction_counter.sv index 2b58410..780b99a 100644 --- a/modules/instruction_counter.sv +++ b/modules/instruction_counter.sv @@ -8,14 +8,14 @@ module instruction_counter #(parameter width=5)( ); logic [2**width-1:0] pc; - always_ff (@posedge clk) begin + always_ff @(posedge clk) begin if (we) begin - pc <= W - else + pc <= W; + end else begin pc <= pc + 4; end end assign addr = pc; endmodule -`endif \ No newline at end of file +`endif diff --git a/modules/ram.sv b/modules/ram.sv index d1199b8..135161a 100644 --- a/modules/ram.sv +++ b/modules/ram.sv @@ -1,4 +1,7 @@ -module rom #(addrwidth=9, datawidth=5)( +`ifndef RAM_H +`define RAM_H + +module ram #(addrwidth=9, datawidth=5)( input logic [0:0] clk, input logic [2**addrwidth-1:0] addr, input logic [0:0] we, @@ -15,11 +18,13 @@ module rom #(addrwidth=9, datawidth=5)( end end - always_ff(@posedge clk) begin + always_ff @(posedge clk) begin if (we) begin mem[addr] <= data_in; end end assign data_out = mem[addr]; -endmodule; \ No newline at end of file +endmodule + +`endif diff --git a/modules/rom.sv b/modules/rom.sv index f22d843..80e6a4b 100644 --- a/modules/rom.sv +++ b/modules/rom.sv @@ -1,3 +1,5 @@ +`ifndef ROM_H +`define ROM_H module rom #(parameter m=7,p=4) ( input logic [m-1:0] Ad, @@ -17,3 +19,5 @@ module rom #(parameter m=7,p=4) ( `endif end endmodule // end rom module + +`endif