Updated assignment 2 dependency modules (currently 8 errors in compile)

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TroubleElectrical committed 2026-10-13 12:23:52 +11:00
1 parent 8675f5b8ee
commit e57e8f362a
17 files changed
+412 -14

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+20 -6
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@@ -1,8 +1,20 @@
`include "rom.sv"
`include "ram.sv"
`include "instruction_counter.sv"
`include "instruction_classifier.sv"
`include "alu.sv"
`ifndef ASS_2_SV
`define ASS_2_SV
`ifdef SYNTHESIS
`include "../../rom.sv"
`include "../../ram.sv"
`include "../../instruction_counter.sv"
`include "../../instruction_classifier.sv"
`include "../../alu.sv"
`else
`include "rom.sv"
`include "ram.sv"
`include "instruction_counter.sv"
`include "instruction_classifier.sv"
`include "alu.sv"
`endif
module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
@@ -16,4 +28,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
RAM ram #(ramsz, 2**width)();
alu alu #(width)();
endmodule
endmodule
`endif