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Updated assignment 2 dependency modules (currently 8 errors in compile)

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TroubleElectrical committed 2026-10-13 12:23:52 +11:00
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Quartus/A2/output_files/assignment2.flow.rpt
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Flow report for assignment2
Tue Oct 13 12:21:52 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------------+-------------------------------------------------+
; Flow Status ; Flow Failed - Tue Oct 13 12:21:52 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total block memory bits ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
; Total DLLs ; N/A until Partition Merge ;
+-----------------------------+-------------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/13/2026 12:21:43 ;
; Main task ; Compilation ;
; Revision Name ; assignment2 ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 268883478169649.179185450204071 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 400 MB ; 00:00:25 ;
; Total ; 00:00:10 ; -- ; -- ; 00:00:25 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+---------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+---------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+---------------------+------------+------------+----------------+
; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
+----------------------+---------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2