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Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

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TroubleElectrical committed 2026-09-09 14:27:11 +10:00
1 parent 5acf1c8b87
commit dc32347c9b
212 files changed
+8657 -71
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Quartus/A1_Q3/asu.qsf
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@@ -54,4 +54,34 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_AC9 -to A[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to A
set_location_assignment PIN_AE10 -to A[1]
set_location_assignment PIN_AD13 -to A[2]
set_location_assignment PIN_AC8 -to A[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to B
set_location_assignment PIN_W11 -to B[0]
set_location_assignment PIN_AB10 -to B[1]
set_location_assignment PIN_V10 -to B[2]
set_location_assignment PIN_AC10 -to B[3]
set_location_assignment PIN_AE19 -to op[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to op[0]
set_location_assignment PIN_L7 -to OUT_CIN[0]
set_location_assignment PIN_F7 -to OUT_1[0]
set_location_assignment PIN_F6 -to OUT_1[1]
set_location_assignment PIN_G6 -to OUT_1[2]
set_location_assignment PIN_G7 -to OUT_1[3]
set_location_assignment PIN_J8 -to COUT[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Quartus/A1_Q3/asu.qws
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Quartus/A1_Q3/c5_pin_model_dump.txt
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io_4iomodule_c5_index: 61gpio_index: 2
io_4iomodule_c5_index: 62gpio_index: 348
io_4iomodule_c5_index: 40gpio_index: 6
io_4iomodule_c5_index: 59gpio_index: 344
io_4iomodule_c5_index: 31gpio_index: 10
io_4iomodule_c5_index: 35gpio_index: 340
io_4iomodule_c5_index: 42gpio_index: 14
io_4iomodule_c5_index: 19gpio_index: 336
io_4iomodule_c5_index: 29gpio_index: 19
io_4iomodule_c5_index: 9gpio_index: 332
io_4iomodule_c5_index: 34gpio_index: 22
io_4iomodule_c5_index: 25gpio_index: 328
io_4iomodule_c5_index: 17gpio_index: 27
io_4iomodule_c5_index: 44gpio_index: 324
io_4iomodule_c5_index: 57gpio_index: 30
io_4iomodule_c5_index: 13gpio_index: 320
io_4iomodule_c5_index: 5gpio_index: 35
io_4iomodule_c5_index: 39gpio_index: 316
io_4iomodule_c5_index: 14gpio_index: 38
io_4iomodule_c5_index: 27gpio_index: 312
io_4iomodule_c5_index: 21gpio_index: 43
io_4iomodule_c5_index: 8gpio_index: 308
io_4iomodule_c5_index: 20gpio_index: 46
io_4iomodule_c5_index: 26gpio_index: 304
io_4iomodule_c5_index: 1gpio_index: 51
io_4iomodule_c5_index: 38gpio_index: 300
io_4iomodule_c5_index: 50gpio_index: 54
io_4iomodule_c5_index: 36gpio_index: 296
io_4iomodule_c5_index: 11gpio_index: 59
io_4iomodule_c5_index: 2gpio_index: 292
io_4iomodule_c5_index: 4gpio_index: 62
io_4iomodule_c5_index: 6gpio_index: 288
io_4iomodule_c5_index: 48gpio_index: 67
io_4iomodule_c5_index: 24gpio_index: 284
io_4iomodule_c5_index: 0gpio_index: 70
io_4iomodule_c5_index: 12gpio_index: 280
io_4iomodule_c5_index: 49gpio_index: 75
io_4iomodule_c5_index: 63gpio_index: 276
io_4iomodule_c5_index: 41gpio_index: 78
io_4iomodule_c5_index: 37gpio_index: 272
io_4iomodule_c5_index: 3gpio_index: 83
io_4iomodule_c5_index: 33gpio_index: 268
io_4iomodule_c5_index: 22gpio_index: 86
io_4iomodule_c5_index: 54gpio_index: 264
io_4iomodule_c5_index: 56gpio_index: 91
io_4iomodule_c5_index: 32gpio_index: 260
io_4iomodule_c5_index: 53gpio_index: 94
io_4iomodule_c5_index: 52gpio_index: 256
io_4iomodule_c5_index: 28gpio_index: 99
io_4iomodule_c5_index: 45gpio_index: 252
io_4iomodule_c5_index: 10gpio_index: 102
io_4iomodule_c5_index: 43gpio_index: 248
io_4iomodule_c5_index: 15gpio_index: 107
io_4iomodule_c5_index: 7gpio_index: 244
io_4iomodule_c5_index: 55gpio_index: 110
io_4iomodule_c5_index: 60gpio_index: 240
io_4iomodule_c5_index: 18gpio_index: 115
io_4iomodule_c5_index: 58gpio_index: 236
io_4iomodule_c5_index: 46gpio_index: 118
io_4iomodule_c5_index: 30gpio_index: 232
io_4iomodule_c5_index: 16gpio_index: 123
io_4iomodule_c5_index: 47gpio_index: 228
io_4iomodule_c5_index: 51gpio_index: 126
io_4iomodule_c5_index: 23gpio_index: 224
io_4iomodule_h_c5_index: 0gpio_index: 129
io_4iomodule_h_c5_index: 18gpio_index: 133
io_4iomodule_h_c5_index: 15gpio_index: 137
io_4iomodule_h_c5_index: 16gpio_index: 141
io_4iomodule_h_c5_index: 20gpio_index: 144
io_4iomodule_h_c5_index: 23gpio_index: 148
io_4iomodule_h_c5_index: 12gpio_index: 152
io_4iomodule_h_c5_index: 9gpio_index: 156
io_4iomodule_h_c5_index: 1gpio_index: 160
io_4iomodule_h_c5_index: 5gpio_index: 164
io_4iomodule_h_c5_index: 21gpio_index: 168
io_4iomodule_h_c5_index: 6gpio_index: 172
io_4iomodule_h_c5_index: 17gpio_index: 176
io_4iomodule_h_c5_index: 2gpio_index: 180
io_4iomodule_h_c5_index: 4gpio_index: 184
io_4iomodule_h_c5_index: 3gpio_index: 188
io_4iomodule_h_c5_index: 14gpio_index: 192
io_4iomodule_h_c5_index: 7gpio_index: 196
io_4iomodule_h_c5_index: 19gpio_index: 200
io_4iomodule_h_c5_index: 11gpio_index: 204
io_4iomodule_h_c5_index: 8gpio_index: 208
io_4iomodule_h_c5_index: 13gpio_index: 212
io_4iomodule_h_c5_index: 22gpio_index: 216
io_4iomodule_h_c5_index: 10gpio_index: 220
Quartus/A1_Q3/db/.cmp.kpt
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Quartus/A1_Q3/db/A1_Q3.map_bb.logdb
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@@ -0,0 +1 @@
v1
Quartus/A1_Q3/db/asu.(0).cnf.cdb
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Quartus/A1_Q3/db/asu.(0).cnf.hdb
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Quartus/A1_Q3/db/asu.asm.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927281761 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927281761 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:14:41 2026 " "Processing started: Wed Sep 9 14:14:41 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927281761 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788927281761 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788927281761 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788927282407 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788927286692 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "511 " "Peak virtual memory: 511 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927286879 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:14:46 2026 " "Processing ended: Wed Sep 9 14:14:46 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927286879 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927286879 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927286879 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788927286879 ""}
Quartus/A1_Q3/db/asu.asm.rdb
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Quartus/A1_Q3/db/asu.cbx.xml
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="asu">
</PROJECT>
</LOG_ROOT>
Quartus/A1_Q3/db/asu.cmp.bpm
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Quartus/A1_Q3/db/asu.cmp.cdb
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Quartus/A1_Q3/db/asu.cmp.hdb
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Quartus/A1_Q3/db/asu.cmp.idb
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Quartus/A1_Q3/db/asu.cmp.logdb
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v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
IO_RULES_MATRIX,Total Pass,0;15;15;0;0;15;15;0;0;0;0;0;0;6;0;0;0;0;6;0;0;0;0;6;0;15;15;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,15;0;0;15;15;0;0;15;15;15;15;15;15;9;15;15;15;15;9;15;15;15;15;9;15;0;0;15,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,OUT_1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,COUT[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,OUT_CIN[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,op[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,A[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,B[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,28,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19,
Quartus/A1_Q3/db/asu.cmp.rdb
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Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Version_Index = 604268800
Creation_Time = Tue Sep 8 15:43:22 2026
Creation_Time = Wed Sep 9 14:00:58 2026
Quartus/A1_Q3/db/asu.eda.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927295080 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927295081 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:14:54 2026 " "Processing started: Wed Sep 9 14:14:54 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927295081 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788927295081 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788927295081 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788927295814 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "asu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/ simulation " "Generated file asu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788927295856 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927295893 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:14:55 2026 " "Processing ended: Wed Sep 9 14:14:55 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927295893 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927295893 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927295893 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788927295893 ""}
Quartus/A1_Q3/db/asu.fit.qmsg
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788927253447 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788927253447 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "asu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"asu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788927253452 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788927253522 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788927253522 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788927253934 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788927253961 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788927254010 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788927260724 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927260744 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788927260746 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788927260746 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788927260746 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788927260746 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788927260747 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788927260747 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788927260747 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788927260747 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788927260747 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:06 " "Fitter preparation operations ending: elapsed time is 00:00:06" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927260764 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788927266566 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788927266566 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788927266567 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788927266567 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788927266568 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788927266568 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788927266569 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788927266571 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788927266670 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927267180 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788927267673 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788927267909 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927267909 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788927268856 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788927274232 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788927274232 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788927274482 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788927274482 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788927274482 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927274485 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788927275578 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788927275619 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788927275980 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788927275980 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788927276713 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927279349 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1788927279608 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1383 " "Peak virtual memory: 1383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927280159 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:14:40 2026 " "Processing ended: Wed Sep 9 14:14:40 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927280159 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927280159 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:38 " "Total CPU time (on all processors): 00:00:38" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927280159 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788927280159 ""}
Quartus/A1_Q3/db/asu.hier_info
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|asu
op[0] => operand[0].IN0
op[0] => operand[1].IN0
op[0] => operand[2].IN0
op[0] => operand[3].IN0
op[0] => _.DATAB
A[0] => _.DATAD
A[1] => _.DATAD
A[2] => _.DATAD
A[3] => OUT_CIN.IN1
A[3] => _.DATAD
B[0] => operand[0].IN1
B[1] => operand[1].IN1
B[2] => operand[2].IN1
B[3] => operand[3].IN1
OUT_1[0] << _.SUM_OUT
OUT_1[1] << _.SUM_OUT
OUT_1[2] << _.SUM_OUT
OUT_1[3] << _.SUM_OUT
COUT[0] << _.SUM_OUT
OUT_CIN[0] << OUT_CIN.DB_MAX_OUTPUT_PORT_TYPE
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Quartus/A1_Q3/db/asu.lpc.html
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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>
Quartus/A1_Q3/db/asu.lpc.rdb
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927241387 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927241387 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:14:01 2026 " "Processing started: Wed Sep 9 14:14:01 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927241387 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927241387 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927241387 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788927241701 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788927241701 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788927250589 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927250589 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "asu " "Elaborating entity \"asu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788927250727 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788927251412 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788927251755 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788927251755 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788927251783 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788927251783 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788927251783 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788927251783 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927251789 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:14:11 2026 " "Processing ended: Wed Sep 9 14:14:11 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927251789 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927251789 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927251789 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927251789 ""}
Quartus/A1_Q3/db/asu.map.rdb
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927288337 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927288337 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:14:48 2026 " "Processing started: Wed Sep 9 14:14:48 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927288337 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788927288337 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q3 -c asu " "Command: quartus_sta A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788927288337 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788927288391 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788927288862 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788927288862 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927288936 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927288937 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788927289506 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927289507 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927289508 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927289508 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788927289509 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927289509 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788927289510 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788927289518 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788927289519 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927289521 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927289525 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927289526 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927289527 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927289528 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927289528 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788927289531 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788927289571 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788927290854 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927290940 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927290940 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927290941 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927290941 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927290941 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927290943 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927290944 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927290945 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927290945 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927290946 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788927290947 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788927291208 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788927291913 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927291955 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927291955 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927291955 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927291955 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927291957 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927291957 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927291958 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927291959 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927291960 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788927291961 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927292109 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927292109 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927292110 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927292110 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927292111 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927292112 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927292112 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927292113 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927292114 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788927293498 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788927293499 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "780 " "Peak virtual memory: 780 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927293525 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:14:53 2026 " "Processing ended: Wed Sep 9 14:14:53 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927293525 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927293525 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927293525 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788927293525 ""}
Quartus/A1_Q3/db/asu.sta.rdb
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start_full_compilation:s:00:00:56
start_analysis_synthesis:s:00:00:12-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:28-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:07-start_full_compilation
start_eda_netlist_writer:s:00:00:02-start_full_compilation
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{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "OUT_1[0]",
"strict" : false
},
{
"name" : "OUT_1[1]",
"strict" : false
},
{
"name" : "OUT_1[2]",
"strict" : false
},
{
"name" : "OUT_1[3]",
"strict" : false
},
{
"name" : "COUT[0]",
"strict" : false
},
{
"name" : "OUT_CIN[0]",
"strict" : false
},
{
"name" : "op[0]",
"strict" : false
},
{
"name" : "A[3]",
"strict" : false
},
{
"name" : "B[3]",
"strict" : false
},
{
"name" : "B[0]",
"strict" : false
},
{
"name" : "A[0]",
"strict" : false
},
{
"name" : "A[1]",
"strict" : false
},
{
"name" : "B[1]",
"strict" : false
},
{
"name" : "A[2]",
"strict" : false
},
{
"name" : "B[2]",
"strict" : false
}
]
}
]
}
Quartus/A1_Q3/db/prev_cmp_A1_Q3.qmsg
+136
View File
@@ -0,0 +1,136 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788926483802 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788926483802 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:01:23 2026 " "Processing started: Wed Sep 9 14:01:23 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788926483802 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788926483802 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788926483802 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788926484135 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788926484135 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788926493817 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788926493817 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "asu " "Elaborating entity \"asu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788926493967 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788926494810 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788926495220 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788926495220 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788926495353 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788926495353 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788926495353 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788926495353 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788926495359 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:01:35 2026 " "Processing ended: Wed Sep 9 14:01:35 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788926495359 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788926495359 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788926495359 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788926495359 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1788926497164 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788926497164 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:01:36 2026 " "Processing started: Wed Sep 9 14:01:36 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788926497164 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1788926497164 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_fit --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1788926497164 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1788926497419 ""}
{ "Info" "0" "" "Project = A1_Q3" { } { } 0 0 "Project = A1_Q3" 0 0 "Fitter" 0 0 1788926497420 ""}
{ "Info" "0" "" "Revision = asu" { } { } 0 0 "Revision = asu" 0 0 "Fitter" 0 0 1788926497420 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788926497623 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788926497623 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "asu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"asu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788926497629 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788926497701 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788926497701 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788926498129 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788926498176 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788926498329 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "15 15 " "No exact pin location assignment(s) for 15 pins of 15 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1788926498595 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788926505300 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926505385 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788926505403 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788926505404 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788926505404 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788926505404 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788926505404 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788926505404 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788926505404 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788926505405 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788926505405 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926505428 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788926511434 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788926511435 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788926511435 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788926511436 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788926511437 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788926511438 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788926511438 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788926511441 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788926511505 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926512859 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788926513888 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788926514218 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926514218 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788926514811 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y24 X68_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36"} { { 12 { 0 ""} 57 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788926520294 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788926520294 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788926520439 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788926520439 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788926520439 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926520441 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788926521315 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788926521347 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788926521727 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788926521728 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788926522272 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788926524805 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1338 " "Peak virtual memory: 1338 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788926525617 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:02:05 2026 " "Processing ended: Wed Sep 9 14:02:05 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788926525617 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Elapsed time: 00:00:29" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788926525617 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788926525617 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788926525617 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1788926527388 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788926527389 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:02:07 2026 " "Processing started: Wed Sep 9 14:02:07 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788926527389 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788926527389 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788926527389 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788926528043 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788926532635 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "517 " "Peak virtual memory: 517 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788926532856 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:02:12 2026 " "Processing ended: Wed Sep 9 14:02:12 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788926532856 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788926532856 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788926532856 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788926532856 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1788926533654 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1788926534483 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788926534483 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:02:14 2026 " "Processing started: Wed Sep 9 14:02:14 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788926534483 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788926534483 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q3 -c asu " "Command: quartus_sta A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788926534483 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788926534543 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788926535026 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788926535026 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926535101 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926535101 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788926535698 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926535698 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788926535698 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788926535699 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788926535699 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788926535699 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788926535700 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788926535704 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788926535704 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535706 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535713 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535714 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535715 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535716 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926535717 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788926535720 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788926535763 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788926536755 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926536841 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788926536841 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788926536841 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788926536842 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536842 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536844 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536845 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536845 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536846 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926536847 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788926536848 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788926537107 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788926537653 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926537695 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788926537695 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788926537695 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788926537695 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537697 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537698 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537698 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537699 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537700 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788926537702 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788926537846 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788926537846 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788926537847 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788926537847 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537848 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537849 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537850 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537850 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788926537851 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788926539453 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788926539453 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "760 " "Peak virtual memory: 760 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788926539482 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:02:19 2026 " "Processing ended: Wed Sep 9 14:02:19 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788926539482 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788926539482 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788926539482 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788926539482 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1788926541113 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788926541114 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:02:20 2026 " "Processing started: Wed Sep 9 14:02:20 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788926541114 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788926541114 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788926541114 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788926541877 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "asu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/ simulation " "Generated file asu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788926541950 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "659 " "Peak virtual memory: 659 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788926541988 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:02:21 2026 " "Processing ended: Wed Sep 9 14:02:21 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788926541988 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788926541988 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788926541988 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788926541988 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus Prime Full Compilation was successful. 0 errors, 15 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788926542651 ""}
Quartus/A1_Q3/incremental_db/README
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
Quartus/A1_Q3/incremental_db/compiled_partitions/asu.db_info
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Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Version_Index = 604268800
Creation_Time = Wed Sep 9 14:01:34 2026
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v1
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Assembler report for asu
Wed Sep 9 14:14:46 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: asu.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Sep 9 14:14:46 2026 ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+-----------------------------------------------------------------------------+
; Assembler Generated Files ;
+-----------------------------------------------------------------------------+
; File Name ;
+-----------------------------------------------------------------------------+
; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/output_files/asu.sof ;
+-----------------------------------------------------------------------------+
+-----------------------------------+
; Assembler Device Options: asu.sof ;
+----------------+------------------+
; Option ; Setting ;
+----------------+------------------+
; JTAG usercode ; 0x00781610 ;
; Checksum ; 0x00781610 ;
+----------------+------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Wed Sep 9 14:14:41 2026
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 511 megabytes
Info: Processing ended: Wed Sep 9 14:14:46 2026
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05
Quartus/A1_Q3/output_files/asu.done
+1
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Wed Sep 9 14:14:56 2026
Quartus/A1_Q3/output_files/asu.eda.rpt
+94
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EDA Netlist Writer report for asu
Wed Sep 9 14:14:55 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Sep 9 14:14:55 2026 ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
; Family ; Cyclone V ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+------------------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+------------------------------------+
; Tool Name ; Questa Altera FPGA (SystemVerilog) ;
; Generate functional simulation netlist ; On ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+------------------------------------+
+----------------------------------------------------------------------------------+
; Simulation Generated Files ;
+----------------------------------------------------------------------------------+
; Generated Files ;
+----------------------------------------------------------------------------------+
; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/asu.svo ;
+----------------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Wed Sep 9 14:14:54 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file asu.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 658 megabytes
Info: Processing ended: Wed Sep 9 14:14:55 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Quartus/A1_Q3/output_files/asu.fit.rpt
+1384
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File diff suppressed because it is too large. Load diff
Quartus/A1_Q3/output_files/asu.fit.summary
+20
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Fitter Status : Successful - Wed Sep 9 14:14:39 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : asu
Top-level Entity Name : asu
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 4 / 29,080 ( < 1 % )
Total registers : 0
Total pins : 15 / 364 ( 4 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )
Total DSP Blocks : 0 / 150 ( 0 % )
Total HSSI RX PCSs : 0 / 6 ( 0 % )
Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % )
Total HSSI TX PCSs : 0 / 6 ( 0 % )
Total HSSI PMA TX Serializers : 0 / 6 ( 0 % )
Total PLLs : 0 / 12 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )
Quartus/A1_Q3/output_files/asu.flow.rpt
+136
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@@ -0,0 +1,136 @@
Flow report for asu
Wed Sep 9 14:14:55 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Wed Sep 9 14:14:55 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 4 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 15 / 364 ( 4 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ;
; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ;
; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ;
; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ;
; Total PLLs ; 0 / 12 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+-------------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/09/2026 14:14:01 ;
; Main task ; Compilation ;
; Revision Name ; asu ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 268883478169649.178892724102952 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 419 MB ; 00:00:24 ;
; Fitter ; 00:00:27 ; 1.0 ; 1383 MB ; 00:00:38 ;
; Assembler ; 00:00:05 ; 1.0 ; 511 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 780 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:00:48 ; -- ; -- ; 00:01:13 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+---------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+---------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+---------------------+------------+------------+----------------+
; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; Fitter ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; Assembler ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; Timing Analyzer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; EDA Netlist Writer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
+----------------------+---------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu
quartus_fit --read_settings_files=off --write_settings_files=off A1_Q3 -c asu
quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu
quartus_sta A1_Q3 -c asu
quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu
Quartus/A1_Q3/output_files/asu.jdi
+8
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@@ -0,0 +1,8 @@
<sld_project_info>
<project>
<hash md5_digest_80b="743a2729e0995dcafc9b"/>
</project>
<file_info>
<file device="5CGXFC5C6F27C7" path="asu.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>
Quartus/A1_Q3/output_files/asu.map.rpt
+294
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@@ -0,0 +1,294 @@
Analysis & Synthesis report for asu
Wed Sep 9 14:14:11 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Parameter Settings for User Entity Instance: Top-level Entity: |asu
10. Post-Synthesis Netlist Statistics for Top Partition
11. Elapsed Time Per Partition
12. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Sep 9 14:14:11 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 0 ;
; Total pins ; 15 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; Total DSP Blocks ; 0 ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI PMA TX Serializers ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+---------------------------------+-------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; 5CGXFC5C6F27C7 ; ;
; Top-level entity name ; asu ; asu ;
; Family name ; Cyclone V ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 3 ; 3 ;
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Automatic Parallel Synthesis ; On ; On ;
; Partial Reconfiguration Bitstream ID ; Off ; Off ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------+---------+
; ../../modules/asu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------+---------+
+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------------+
; Resource ; Usage ;
+---------------------------------------------+-------------+
; Estimate of Logic utilization (ALMs needed) ; 3 ;
; ; ;
; Combinational ALUT usage for logic ; 6 ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 0 ;
; -- 5 input functions ; 0 ;
; -- 4 input functions ; 1 ;
; -- <=3 input functions ; 5 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 15 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; op[0]~input ;
; Maximum fan-out ; 5 ;
; Total fan-out ; 41 ;
; Average fan-out ; 1.14 ;
+---------------------------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; |asu ; 6 (6) ; 0 (0) ; 0 ; 0 ; 15 ; 0 ; |asu ; asu ; work ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |asu ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------+
; width ; 2 ; Signed Integer ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_lcell_comb ; 6 ;
; normal ; 1 ;
; 4 data inputs ; 1 ;
; shared ; 5 ;
; 0 data inputs ; 1 ;
; 3 data inputs ; 4 ;
; boundary_port ; 15 ;
; ; ;
; Max LUT depth ; 2.30 ;
; Average LUT depth ; 1.95 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Wed Sep 9 14:14:01 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv
Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 1
Info (12127): Elaborating entity "asu" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 21 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 9 input pins
Info (21059): Implemented 6 output pins
Info (21061): Implemented 6 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 433 megabytes
Info: Processing ended: Wed Sep 9 14:14:11 2026
Info: Elapsed time: 00:00:10
Info: Total CPU time (on all processors): 00:00:24
Quartus/A1_Q3/output_files/asu.map.summary
+17
View File
@@ -0,0 +1,17 @@
Analysis & Synthesis Status : Successful - Wed Sep 9 14:14:11 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : asu
Top-level Entity Name : asu
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 15
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0
Total DLLs : 0
Quartus/A1_Q3/output_files/asu.pin
+750
View File
@@ -0,0 +1,750 @@
-- Copyright (C) 2025 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 3A: 2.5V
-- Bank 3B: 1.2V
-- Bank 4A: 1.2V
-- Bank 5A: 2.5V
-- Bank 5B: 2.5V
-- Bank 6A: 2.5V
-- Bank 7A: 2.5V
-- Bank 8A: 2.5V
-- Bank 9A: Dedicated configuration pins only, no VCCIO required.
-- RREF : External reference resistor for the quad, MUST be connected to
-- GND via a 2k Ohm resistor.
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND*
-- either individually through a 10k Ohm resistor to GND or tie all pins
-- together and connect through a single 10k Ohm resistor to GND.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
-- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
-- must not be connected.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
CHIP "asu" ASSIGNED TO AN: 5CGXFC5C6F27C7
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
MSEL2 : A2 : : : : 9A :
DNU : A3 : : : : :
DNU : A4 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
CONF_DONE : A6 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7A :
VCCIO7A : A10 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7A :
GND : A15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A :
VCCIO7A : A20 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
GND : A25 : gnd : : : :
GND : AA1 : gnd : : : :
GND : AA2 : gnd : : : :
GXB_NC : AA3 : : : : B0L :
GXB_NC : AA4 : : : : B0L :
GND : AA5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A :
VCC_AUX : AA8 : power : : 2.5V : :
VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : :
VCCIO3B : AA10 : power : : 1.2V : 3B :
VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A :
NC : AA12 : : : : :
VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4A :
GND : AA15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A :
VCCIO4A : AA20 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5B :
GND : AA25 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
GND : AB1 : : : : B0L :
GND : AB2 : : : : B0L :
GND : AB3 : gnd : : : :
GND : AB4 : gnd : : : :
AS_DATA2, DATA2 : AB5 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3A :
NC : AB7 : : : : :
GND : AB8 : gnd : : : :
VCCPD3A : AB9 : power : : 2.5V : 3A :
B[1] : AB10 : input : 1.2 V : : 3B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B :
VCCIO4A : AB13 : power : : 1.2V : 4A :
VCC_AUX : AB14 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
GND : AB18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4A :
VCC_AUX : AB20 : power : : 2.5V : :
VCCPD3B4A : AB21 : power : : 2.5V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4A :
VCCIO5A : AB23 : power : : 2.5V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5B :
GND : AC1 : gnd : : : :
GND : AC2 : gnd : : : :
GXB_NC : AC3 : : : : B0L :
GXB_NC : AC4 : : : : B0L :
GND : AC5 : gnd : : : :
VCCIO3A : AC6 : power : : 2.5V : 3A :
VREFB3AN0 : AC7 : power : : : 3A :
A[3] : AC8 : input : 1.2 V : : 3B : Y
A[0] : AC9 : input : 1.2 V : : 3B : Y
B[3] : AC10 : input : 1.2 V : : 3B : Y
GND : AC11 : gnd : : : :
VREFB3BN0 : AC12 : power : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A :
VCCIO4A : AC16 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
GND : AC21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5B :
GND : AC26 : gnd : : : :
GND : AD1 : : : : B0L :
GND : AD2 : : : : B0L :
GND : AD3 : gnd : : : :
GND : AD4 : gnd : : : :
AS_DATA1, DATA1 : AD5 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B :
VCCIO3B : AD9 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A :
A[2] : AD13 : input : 1.2 V : : 4A : Y
GND : AD14 : gnd : : : :
VREFB4AN0 : AD15 : power : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A :
VCCIO4A : AD19 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A :
GND : AD24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 4A :
GND : AE1 : gnd : : : :
GND : AE2 : gnd : : : :
GXB_NC : AE3 : : : : B0L :
GXB_NC : AE4 : : : : B0L :
GND : AE5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3B :
GND : AE7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B :
A[1] : AE10 : input : 1.2 V : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A :
VCCIO4A : AE12 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
GND : AE17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
op[0] : AE19 : input : 1.2 V : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A :
VCCIO4A : AE22 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 4A :
GND : AF2 : gnd : : : :
GND : AF3 : gnd : : : :
GND : AF4 : gnd : : : :
AS_DATA0, ASDO, DATA0 : AF5 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B :
GND : AF10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A :
VCCIO4A : AF15 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
GND : AF20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
GND : AF25 : gnd : : : :
RREF : B1 : : : : :
GND : B2 : gnd : : : :
GND : B3 : gnd : : : :
GND : B4 : gnd : : : :
nSTATUS : B5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
GND : B8 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7A :
VCCIO7A : B13 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7A :
VREFB7AN0 : B16 : power : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7A :
GND : B18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
VCCIO7A : B23 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A :
GND : C1 : gnd : : : :
GND : C2 : gnd : : : :
NC : C3 : : : : :
NC : C4 : : : : :
GND : C5 : gnd : : : :
VCCIO8A : C6 : power : : 2.5V : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
VREFB8AN0 : C8 : power : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7A :
GND : C11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7A :
VCCIO7A : C16 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7A :
GND : C21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
DNU : C24 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 6A :
VCCIO6A : C26 : power : : 2.5V : 6A :
NC : D1 : : : : :
NC : D2 : : : : :
GND : D3 : gnd : : : :
GND : D4 : gnd : : : :
nCE : D5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8A :
VCCIO8A : D9 : power : : 2.5V : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7A :
GND : D14 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7A :
VCCIO7A : D19 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6A :
GND : D23 : : : : 7A :
GND : D24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6A :
GND : E1 : gnd : : : :
GND : E2 : gnd : : : :
NC : E3 : : : : :
NC : E4 : : : : :
GND : E5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
GND : E7 : gnd : : : :
VCCBAT : E8 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7A :
VCCIO7A : E12 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7A :
VCC_AUX : E14 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7A :
GND : E17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6A :
VCCIO6A : E22 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6A :
NC : F1 : : : : :
NC : F2 : : : : :
GND : F3 : gnd : : : :
GND : F4 : gnd : : : :
nCONFIG : F5 : : : : 9A :
OUT_1[1] : F6 : output : 2.5 V : : 8A : Y
OUT_1[0] : F7 : output : 2.5 V : : 8A : Y
VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : :
VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A :
GND : F10 : gnd : : : :
VCCPD7A8A : F11 : power : : 2.5V : 7A, 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7A :
VCCPD7A8A : F13 : power : : 2.5V : 7A, 8A :
DNU : F14 : : : : :
VCCIO7A : F15 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7A :
VCCPD7A8A : F17 : power : : 2.5V : 7A, 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7A :
VCCPD7A8A : F19 : power : : 2.5V : 7A, 8A :
GND : F20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6A :
VCCIO6A : F25 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
GND : G1 : gnd : : : :
GND : G2 : gnd : : : :
NC : G3 : : : : :
NC : G4 : : : : :
GND : G5 : gnd : : : :
OUT_1[2] : G6 : output : 2.5 V : : 8A : Y
OUT_1[3] : G7 : output : 2.5 V : : 8A : Y
VCCIO8A : G8 : power : : 2.5V : 8A :
VCC_AUX : G9 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 7A :
GND : G13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7A :
VCCIO7A : G18 : power : : 2.5V : 7A :
VCC_AUX : G19 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6A :
VCCA_FPLL : G21 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6A :
GND : G23 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
NC : H1 : : : : :
NC : H2 : : : : :
GND : H3 : gnd : : : :
GND : H4 : gnd : : : :
GND : H5 : : : : 9A :
GND : H6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8A :
VCCIO7A : H11 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7A :
GND : H16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6A :
VCCIO6A : H21 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
GND : H26 : gnd : : : :
GND : J1 : gnd : : : :
GND : J2 : gnd : : : :
VCCL_GXBL : J3 : power : : 1.1V : :
GND : J4 : gnd : : : :
MSEL4 : J5 : : : : 9A :
VCCA_FPLL : J6 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
COUT[0] : J8 : output : 2.5 V : : 8A : Y
GND : J9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7A :
VCC : J13 : power : : 1.1V : :
GND : J14 : gnd : : : :
VCC : J15 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7A :
VCC : J17 : power : : 1.1V : :
GND : J18 : gnd : : : :
VCC : J19 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6A :
VCCPD6A : J22 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
VCCIO6A : J24 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
GXB_NC : K1 : : : : B1L :
GXB_NC : K2 : : : : B1L :
GND : K3 : gnd : : : :
VCCE_GXBL : K4 : power : : 1.1V : :
MSEL3 : K5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 8A :
VCCIO8A : K7 : power : : 2.5V : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 7A :
GND : K12 : gnd : : : :
GND : K13 : gnd : : : :
VCC : K14 : power : : 1.1V : :
GND : K15 : gnd : : : :
VCC : K16 : power : : 1.1V : :
GND : K17 : gnd : : : :
VCC : K18 : power : : 1.1V : :
GND : K19 : gnd : : : :
VCC : K20 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
GND : K22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
GND : L1 : gnd : : : :
GND : L2 : gnd : : : :
VCCH_GXBL : L3 : power : : 2.5V : :
GND : L4 : gnd : : : :
NC : L5 : : : : :
MSEL1 : L6 : : : : 9A :
OUT_CIN[0] : L7 : output : 2.5 V : : 8A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 8A :
GND : L10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L12 : : : : 7A :
VCC : L13 : power : : 1.1V : :
GND : L14 : gnd : : : :
VCC : L15 : power : : 1.1V : :
GND : L16 : gnd : : : :
VCC : L17 : power : : 1.1V : :
GND : L18 : gnd : : : :
VCC : L19 : power : : 1.1V : :
GND : L20 : gnd : : : :
VCCPD6A : L21 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
GND : L25 : gnd : : : :
VREFB6AN0 : L26 : power : : : 6A :
GND : M1 : : : : B1L :
GND : M2 : : : : B1L :
GND : M3 : gnd : : : :
VCCE_GXBL : M4 : power : : 1.1V : :
GND : M5 : gnd : : : :
NC : M6 : : : : :
MSEL0 : M7 : : : : 9A :
GND : M8 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M12 : : : : 7A :
GND : M13 : gnd : : : :
VCC : M14 : power : : 1.1V : :
GND : M15 : gnd : : : :
VCC : M16 : power : : 1.1V : :
GND : M17 : gnd : : : :
VCC : M18 : power : : 1.1V : :
GND : M19 : gnd : : : :
VCC : M20 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
VCCIO6A : M23 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
GND : N1 : gnd : : : :
GND : N2 : gnd : : : :
VCCL_GXBL : N3 : power : : 1.1V : :
GND : N4 : gnd : : : :
VCCE_GXBL : N5 : power : : 1.1V : :
GND : N6 : gnd : : : :
GND : N7 : : : : B1L :
DCLK : N8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N10 : : : : 3B :
GND : N11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 7A :
VCC : N13 : power : : 1.1V : :
GND : N14 : gnd : : : :
VCC : N15 : power : : 1.1V : :
GND : N16 : gnd : : : :
VCC : N17 : power : : 1.1V : :
GND : N18 : gnd : : : :
VCC : N19 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6A :
GND : N21 : gnd : : : :
VCCPD5B : N22 : power : : 2.5V : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 5B :
VCCIO5B : N26 : power : : 2.5V : 5B :
GXB_NC : P1 : : : : B1L :
GXB_NC : P2 : : : : B1L :
GND : P3 : gnd : : : :
VCCE_GXBL : P4 : power : : 1.1V : :
GND : P5 : gnd : : : :
GND : P6 : : : : B1L :
GND : P7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3A :
GND : P9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 3B :
GND : P13 : gnd : : : :
VCC : P14 : power : : 1.1V : :
GND : P15 : gnd : : : :
VCC : P16 : power : : 1.1V : :
GND : P17 : gnd : : : :
VCC : P18 : power : : 1.1V : :
GND : P19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P23 : : : : 5B :
GND : P24 : gnd : : : :
VREFB5BN0 : P25 : power : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 5B :
GND : R1 : gnd : : : :
GND : R2 : gnd : : : :
VCCH_GXBL : R3 : power : : 2.5V : :
GND : R4 : gnd : : : :
VCCE_GXBL : R5 : power : : 1.1V : :
TMS : R6 : input : : : 3A :
GND : R7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3B :
GND : R12 : gnd : : : :
VCC : R13 : power : : 1.1V : :
GND : R14 : gnd : : : :
VCC : R15 : power : : 1.1V : :
GND : R16 : gnd : : : :
VCC : R17 : power : : 1.1V : :
GND : R18 : gnd : : : :
VCC : R19 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5B :
VCCPD5B : R21 : power : : 2.5V : 5B :
VCCIO5B : R22 : power : : 2.5V : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5B :
GND : T1 : : : : B1L :
GND : T2 : : : : B1L :
GND : T3 : gnd : : : :
VCCH_GXBL : T4 : power : : 2.5V : :
GND : T5 : gnd : : : :
TDI : T6 : input : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3B :
GND : T10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 3B :
VCC : T14 : power : : 1.1V : :
GND : T15 : gnd : : : :
VCC : T16 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 4A :
VCC : T18 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5A :
GND : T20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 5B :
VCCIO5B : T25 : power : : 2.5V : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5B :
GND : U1 : gnd : : : :
GND : U2 : gnd : : : :
VCCL_GXBL : U3 : power : : 1.1V : :
GND : U4 : gnd : : : :
VCCE_GXBL : U5 : power : : 1.1V : :
AS_DATA3, DATA3 : U6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A :
VCCIO3B : U8 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4A :
GND : U13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A :
VCCIO4A : U18 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A :
VCCPD5A : U21 : power : : 2.5V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A :
GND : U23 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5B :
GND : V1 : : : : B1L :
GND : V2 : : : : B1L :
GND : V3 : gnd : : : :
GND : V4 : gnd : : : :
GND : V5 : gnd : : : :
GND : V6 : : : : B0L :
TDO : V7 : output : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B :
B[2] : V10 : input : 1.2 V : : 3B : Y
VCCIO3B : V11 : power : : 1.2V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A :
GND : V16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A :
VCCIO5A : V21 : power : : 2.5V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
GND : V26 : gnd : : : :
GND : W1 : gnd : : : :
GND : W2 : gnd : : : :
GXB_NC : W3 : : : : B1L :
GXB_NC : W4 : : : : B1L :
GND : W5 : gnd : : : :
GND : W6 : : : : B0L :
VCCA_FPLL : W7 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A :
GND : W9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B :
B[0] : W11 : input : 1.2 V : : 3B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A :
VCCIO4A : W14 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4A :
GND : W19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : :
VREFB5AN0 : W23 : power : : : 5A :
VCCIO5B : W24 : power : : 2.5V : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5B :
GND : Y1 : : : : B0L :
GND : Y2 : : : : B0L :
GND : Y3 : gnd : : : :
GND : Y4 : gnd : : : :
TCK : Y5 : input : : : 3A :
nCSO, DATA4 : Y6 : : : : 3A :
VCCIO3A : Y7 : power : : 2.5V : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B :
GND : Y12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A :
VCCIO4A : Y17 : power : : 1.2V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A :
VCCA_FPLL : Y21 : power : : 2.5V : :
GND : Y22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
Quartus/A1_Q3/output_files/asu.sld
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Quartus/A1_Q3/output_files/asu.sof
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Timing Analyzer report for asu
Wed Sep 9 14:14:53 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1100mV 85C Model Fmax Summary
6. Timing Closure Recommendations
7. Slow 1100mV 85C Model Setup Summary
8. Slow 1100mV 85C Model Hold Summary
9. Slow 1100mV 85C Model Recovery Summary
10. Slow 1100mV 85C Model Removal Summary
11. Slow 1100mV 85C Model Minimum Pulse Width Summary
12. Slow 1100mV 85C Model Metastability Summary
13. Slow 1100mV 0C Model Fmax Summary
14. Slow 1100mV 0C Model Setup Summary
15. Slow 1100mV 0C Model Hold Summary
16. Slow 1100mV 0C Model Recovery Summary
17. Slow 1100mV 0C Model Removal Summary
18. Slow 1100mV 0C Model Minimum Pulse Width Summary
19. Slow 1100mV 0C Model Metastability Summary
20. Fast 1100mV 85C Model Setup Summary
21. Fast 1100mV 85C Model Hold Summary
22. Fast 1100mV 85C Model Recovery Summary
23. Fast 1100mV 85C Model Removal Summary
24. Fast 1100mV 85C Model Minimum Pulse Width Summary
25. Fast 1100mV 85C Model Metastability Summary
26. Fast 1100mV 0C Model Setup Summary
27. Fast 1100mV 0C Model Hold Summary
28. Fast 1100mV 0C Model Recovery Summary
29. Fast 1100mV 0C Model Removal Summary
30. Fast 1100mV 0C Model Minimum Pulse Width Summary
31. Fast 1100mV 0C Model Metastability Summary
32. Multicorner Timing Analysis Summary
33. Board Trace Model Assignments
34. Input Transition Times
35. Signal Integrity Metrics (Slow 1100mv 0c Model)
36. Signal Integrity Metrics (Slow 1100mv 85c Model)
37. Signal Integrity Metrics (Fast 1100mv 0c Model)
38. Signal Integrity Metrics (Fast 1100mv 85c Model)
39. Clock Transfers
40. Report TCCS
41. Report RSKM
42. Unconstrained Paths Summary
43. Unconstrained Input Ports
44. Unconstrained Output Ports
45. Unconstrained Input Ports
46. Unconstrained Output Ports
47. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+---------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+---------------------------------------------------------+
; Quartus Prime Version ; Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; asu ;
; Device Family ; Cyclone V ;
; Device Name ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+---------------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.02 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 2.3% ;
+----------------------------+-------------+
----------
; Clocks ;
----------
No clocks to report.
--------------------------------------
; Slow 1100mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
---------------------------------------
; Slow 1100mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
--------------------------------------
; Slow 1100mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
------------------------------------------
; Slow 1100mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1100mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
-----------------------------------------------------
; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
-----------------------------------------------
; Slow 1100mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
-------------------------------------
; Slow 1100mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.
--------------------------------------
; Slow 1100mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Slow 1100mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Slow 1100mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1100mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Slow 1100mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
---------------------------------------
; Fast 1100mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
--------------------------------------
; Fast 1100mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
------------------------------------------
; Fast 1100mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Fast 1100mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
-----------------------------------------------------
; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
-----------------------------------------------
; Fast 1100mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
--------------------------------------
; Fast 1100mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Fast 1100mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Fast 1100mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1100mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Fast 1100mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+------------------+-------+------+----------+---------+---------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; OUT_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; COUT[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; OUT_CIN[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+----------------------------------------------------------+
; Input Transition Times ;
+-------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------+--------------+-----------------+-----------------+
; op[0] ; 1.2 V ; 960 ps ; 960 ps ;
; A[3] ; 1.2 V ; 960 ps ; 960 ps ;
; B[3] ; 1.2 V ; 960 ps ; 960 ps ;
; B[0] ; 1.2 V ; 960 ps ; 960 ps ;
; A[0] ; 1.2 V ; 960 ps ; 960 ps ;
; A[1] ; 1.2 V ; 960 ps ; 960 ps ;
; B[1] ; 1.2 V ; 960 ps ; 960 ps ;
; A[2] ; 1.2 V ; 960 ps ; 960 ps ;
; B[2] ; 1.2 V ; 960 ps ; 960 ps ;
+-------+--------------+-----------------+-----------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 9 ; 9 ;
; Unconstrained Input Port Paths ; 41 ; 41 ;
; Unconstrained Output Ports ; 6 ; 6 ;
; Unconstrained Output Port Paths ; 41 ; 41 ;
+---------------------------------+-------+------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Wed Sep 9 14:14:48 2026
Info: Command: quartus_sta A1_Q3 -c asu
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1100mV 85C Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Slow 1100mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1100mV 85C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1100mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 780 megabytes
Info: Processing ended: Wed Sep 9 14:14:53 2026
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05
Quartus/A1_Q3/output_files/asu.sta.summary
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Timing Analyzer Summary
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Quartus/A1_Q3/simulation/questa/asu.sft
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set tool_name "Questa Altera FPGA (SystemVerilog)"
Quartus/A1_Q3/simulation/questa/asu.svo
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// Copyright (C) 2025 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Altera and sold by Altera or its authorized distributors. Please
// refer to the Altera Software License Subscription Agreements
// on the Quartus Prime software download page.
// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
// DATE "09/09/2026 14:14:55"
//
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
//
//
// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
//
`timescale 1 ps/ 1 ps
module asu (
op,
A,
B,
OUT_1,
COUT,
OUT_CIN);
input [0:0] op;
input [3:0] A;
input [3:0] B;
output [3:0] OUT_1;
output [0:0] COUT;
output [0:0] OUT_CIN;
// Design Ports Information
// OUT_1[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default
// OUT_1[1] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default
// OUT_1[2] => Location: PIN_G6, I/O Standard: 2.5 V, Current Strength: Default
// OUT_1[3] => Location: PIN_G7, I/O Standard: 2.5 V, Current Strength: Default
// COUT[0] => Location: PIN_J8, I/O Standard: 2.5 V, Current Strength: Default
// OUT_CIN[0] => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default
// op[0] => Location: PIN_AE19, I/O Standard: 1.2 V, Current Strength: Default
// A[3] => Location: PIN_AC8, I/O Standard: 1.2 V, Current Strength: Default
// B[3] => Location: PIN_AC10, I/O Standard: 1.2 V, Current Strength: Default
// B[0] => Location: PIN_W11, I/O Standard: 1.2 V, Current Strength: Default
// A[0] => Location: PIN_AC9, I/O Standard: 1.2 V, Current Strength: Default
// A[1] => Location: PIN_AE10, I/O Standard: 1.2 V, Current Strength: Default
// B[1] => Location: PIN_AB10, I/O Standard: 1.2 V, Current Strength: Default
// A[2] => Location: PIN_AD13, I/O Standard: 1.2 V, Current Strength: Default
// B[2] => Location: PIN_V10, I/O Standard: 1.2 V, Current Strength: Default
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \op[0]~input_o ;
wire \A[0]~input_o ;
wire \B[0]~input_o ;
wire \_~1_sumout ;
wire \A[1]~input_o ;
wire \B[1]~input_o ;
wire \_~2 ;
wire \_~3 ;
wire \_~5_sumout ;
wire \A[2]~input_o ;
wire \B[2]~input_o ;
wire \_~6 ;
wire \_~7 ;
wire \_~9_sumout ;
wire \A[3]~input_o ;
wire \B[3]~input_o ;
wire \_~10 ;
wire \_~11 ;
wire \_~13_sumout ;
wire \_~14 ;
wire \_~15 ;
wire \_~17_sumout ;
wire \OUT_CIN~0_combout ;
// Location: IOOBUF_X14_Y61_N53
cyclonev_io_obuf \OUT_1[0]~output (
.i(\_~1_sumout ),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(OUT_1[0]),
.obar());
// synopsys translate_off
defparam \OUT_1[0]~output .bus_hold = "false";
defparam \OUT_1[0]~output .open_drain_output = "false";
defparam \OUT_1[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X15_Y61_N36
cyclonev_io_obuf \OUT_1[1]~output (
.i(\_~5_sumout ),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(OUT_1[1]),
.obar());
// synopsys translate_off
defparam \OUT_1[1]~output .bus_hold = "false";
defparam \OUT_1[1]~output .open_drain_output = "false";
defparam \OUT_1[1]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X15_Y61_N53
cyclonev_io_obuf \OUT_1[2]~output (
.i(\_~9_sumout ),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(OUT_1[2]),
.obar());
// synopsys translate_off
defparam \OUT_1[2]~output .bus_hold = "false";
defparam \OUT_1[2]~output .open_drain_output = "false";
defparam \OUT_1[2]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X14_Y61_N36
cyclonev_io_obuf \OUT_1[3]~output (
.i(\_~13_sumout ),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(OUT_1[3]),
.obar());
// synopsys translate_off
defparam \OUT_1[3]~output .bus_hold = "false";
defparam \OUT_1[3]~output .open_drain_output = "false";
defparam \OUT_1[3]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X14_Y61_N19
cyclonev_io_obuf \COUT[0]~output (
.i(\_~17_sumout ),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(COUT[0]),
.obar());
// synopsys translate_off
defparam \COUT[0]~output .bus_hold = "false";
defparam \COUT[0]~output .open_drain_output = "false";
defparam \COUT[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X10_Y61_N42
cyclonev_io_obuf \OUT_CIN[0]~output (
.i(\OUT_CIN~0_combout ),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(OUT_CIN[0]),
.obar());
// synopsys translate_off
defparam \OUT_CIN[0]~output .bus_hold = "false";
defparam \OUT_CIN[0]~output .open_drain_output = "false";
defparam \OUT_CIN[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOIBUF_X50_Y0_N35
cyclonev_io_ibuf \op[0]~input (
.i(op[0]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\op[0]~input_o ));
// synopsys translate_off
defparam \op[0]~input .bus_hold = "false";
defparam \op[0]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X14_Y0_N35
cyclonev_io_ibuf \A[0]~input (
.i(A[0]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\A[0]~input_o ));
// synopsys translate_off
defparam \A[0]~input .bus_hold = "false";
defparam \A[0]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X10_Y0_N41
cyclonev_io_ibuf \B[0]~input (
.i(B[0]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\B[0]~input_o ));
// synopsys translate_off
defparam \B[0]~input .bus_hold = "false";
defparam \B[0]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LABCELL_X18_Y4_N30
cyclonev_lcell_comb \_~1 (
// Equation(s):
// \_~1_sumout = SUM(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
// \_~2 = CARRY(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
// \_~3 = SHARE((!\B[0]~input_o & (\op[0]~input_o )) # (\B[0]~input_o & ((\A[0]~input_o ))))
.dataa(gnd),
.datab(!\op[0]~input_o ),
.datac(!\A[0]~input_o ),
.datad(!\B[0]~input_o ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\_~1_sumout ),
.cout(\_~2 ),
.shareout(\_~3 ));
// synopsys translate_off
defparam \_~1 .extended_lut = "off";
defparam \_~1 .lut_mask = 64'h0000330F00000FF0;
defparam \_~1 .shared_arith = "on";
// synopsys translate_on
// Location: IOIBUF_X36_Y0_N52
cyclonev_io_ibuf \A[1]~input (
.i(A[1]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\A[1]~input_o ));
// synopsys translate_off
defparam \A[1]~input .bus_hold = "false";
defparam \A[1]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X12_Y0_N35
cyclonev_io_ibuf \B[1]~input (
.i(B[1]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\B[1]~input_o ));
// synopsys translate_off
defparam \B[1]~input .bus_hold = "false";
defparam \B[1]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LABCELL_X18_Y4_N33
cyclonev_lcell_comb \_~5 (
// Equation(s):
// \_~5_sumout = SUM(( !\A[1]~input_o $ (!\op[0]~input_o $ (\B[1]~input_o )) ) + ( \_~3 ) + ( \_~2 ))
// \_~6 = CARRY(( !\A[1]~input_o $ (!\op[0]~input_o $ (\B[1]~input_o )) ) + ( \_~3 ) + ( \_~2 ))
// \_~7 = SHARE((\A[1]~input_o & (!\op[0]~input_o $ (!\B[1]~input_o ))))
.dataa(!\A[1]~input_o ),
.datab(!\op[0]~input_o ),
.datac(!\B[1]~input_o ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\_~2 ),
.sharein(\_~3 ),
.combout(),
.sumout(\_~5_sumout ),
.cout(\_~6 ),
.shareout(\_~7 ));
// synopsys translate_off
defparam \_~5 .extended_lut = "off";
defparam \_~5 .lut_mask = 64'h0000141400006969;
defparam \_~5 .shared_arith = "on";
// synopsys translate_on
// Location: IOIBUF_X34_Y0_N35
cyclonev_io_ibuf \A[2]~input (
.i(A[2]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\A[2]~input_o ));
// synopsys translate_off
defparam \A[2]~input .bus_hold = "false";
defparam \A[2]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X17_Y0_N75
cyclonev_io_ibuf \B[2]~input (
.i(B[2]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\B[2]~input_o ));
// synopsys translate_off
defparam \B[2]~input .bus_hold = "false";
defparam \B[2]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LABCELL_X18_Y4_N36
cyclonev_lcell_comb \_~9 (
// Equation(s):
// \_~9_sumout = SUM(( !\op[0]~input_o $ (!\A[2]~input_o $ (\B[2]~input_o )) ) + ( \_~7 ) + ( \_~6 ))
// \_~10 = CARRY(( !\op[0]~input_o $ (!\A[2]~input_o $ (\B[2]~input_o )) ) + ( \_~7 ) + ( \_~6 ))
// \_~11 = SHARE((\A[2]~input_o & (!\op[0]~input_o $ (!\B[2]~input_o ))))
.dataa(gnd),
.datab(!\op[0]~input_o ),
.datac(!\A[2]~input_o ),
.datad(!\B[2]~input_o ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\_~6 ),
.sharein(\_~7 ),
.combout(),
.sumout(\_~9_sumout ),
.cout(\_~10 ),
.shareout(\_~11 ));
// synopsys translate_off
defparam \_~9 .extended_lut = "off";
defparam \_~9 .lut_mask = 64'h0000030C00003CC3;
defparam \_~9 .shared_arith = "on";
// synopsys translate_on
// Location: IOIBUF_X14_Y0_N52
cyclonev_io_ibuf \A[3]~input (
.i(A[3]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\A[3]~input_o ));
// synopsys translate_off
defparam \A[3]~input .bus_hold = "false";
defparam \A[3]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X12_Y0_N52
cyclonev_io_ibuf \B[3]~input (
.i(B[3]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\B[3]~input_o ));
// synopsys translate_off
defparam \B[3]~input .bus_hold = "false";
defparam \B[3]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LABCELL_X18_Y4_N39
cyclonev_lcell_comb \_~13 (
// Equation(s):
// \_~13_sumout = SUM(( !\op[0]~input_o $ (!\A[3]~input_o $ (\B[3]~input_o )) ) + ( \_~11 ) + ( \_~10 ))
// \_~14 = CARRY(( !\op[0]~input_o $ (!\A[3]~input_o $ (\B[3]~input_o )) ) + ( \_~11 ) + ( \_~10 ))
// \_~15 = SHARE((\A[3]~input_o & (!\op[0]~input_o $ (!\B[3]~input_o ))))
.dataa(gnd),
.datab(!\op[0]~input_o ),
.datac(!\A[3]~input_o ),
.datad(!\B[3]~input_o ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\_~10 ),
.sharein(\_~11 ),
.combout(),
.sumout(\_~13_sumout ),
.cout(\_~14 ),
.shareout(\_~15 ));
// synopsys translate_off
defparam \_~13 .extended_lut = "off";
defparam \_~13 .lut_mask = 64'h0000030C00003CC3;
defparam \_~13 .shared_arith = "on";
// synopsys translate_on
// Location: LABCELL_X18_Y4_N42
cyclonev_lcell_comb \_~17 (
// Equation(s):
// \_~17_sumout = SUM(( GND ) + ( \_~15 ) + ( \_~14 ))
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\_~14 ),
.sharein(\_~15 ),
.combout(),
.sumout(\_~17_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \_~17 .extended_lut = "off";
defparam \_~17 .lut_mask = 64'h0000000000000000;
defparam \_~17 .shared_arith = "on";
// synopsys translate_on
// Location: LABCELL_X18_Y4_N0
cyclonev_lcell_comb \OUT_CIN~0 (
// Equation(s):
// \OUT_CIN~0_combout = ( \B[3]~input_o & ( \op[0]~input_o & ( !\_~13_sumout $ (!\A[3]~input_o ) ) ) ) # ( !\B[3]~input_o & ( \op[0]~input_o & ( !\_~13_sumout $ (\A[3]~input_o ) ) ) ) # ( \B[3]~input_o & ( !\op[0]~input_o & ( !\_~13_sumout $
// (\A[3]~input_o ) ) ) ) # ( !\B[3]~input_o & ( !\op[0]~input_o & ( !\_~13_sumout $ (!\A[3]~input_o ) ) ) )
.dataa(gnd),
.datab(!\_~13_sumout ),
.datac(gnd),
.datad(!\A[3]~input_o ),
.datae(!\B[3]~input_o ),
.dataf(!\op[0]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\OUT_CIN~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \OUT_CIN~0 .extended_lut = "off";
defparam \OUT_CIN~0 .lut_mask = 64'h33CCCC33CC3333CC;
defparam \OUT_CIN~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X42_Y27_N0
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\~QUARTUS_CREATED_GND~I_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
// synopsys translate_on
endmodule