541 lines
57 KiB
Plaintext
541 lines
57 KiB
Plaintext
Timing Analyzer report for asu
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Wed Sep 9 14:14:53 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Timing Analyzer Summary
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3. Parallel Compilation
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4. Clocks
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5. Slow 1100mV 85C Model Fmax Summary
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6. Timing Closure Recommendations
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7. Slow 1100mV 85C Model Setup Summary
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8. Slow 1100mV 85C Model Hold Summary
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9. Slow 1100mV 85C Model Recovery Summary
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10. Slow 1100mV 85C Model Removal Summary
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11. Slow 1100mV 85C Model Minimum Pulse Width Summary
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12. Slow 1100mV 85C Model Metastability Summary
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13. Slow 1100mV 0C Model Fmax Summary
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14. Slow 1100mV 0C Model Setup Summary
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15. Slow 1100mV 0C Model Hold Summary
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16. Slow 1100mV 0C Model Recovery Summary
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17. Slow 1100mV 0C Model Removal Summary
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18. Slow 1100mV 0C Model Minimum Pulse Width Summary
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19. Slow 1100mV 0C Model Metastability Summary
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20. Fast 1100mV 85C Model Setup Summary
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21. Fast 1100mV 85C Model Hold Summary
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22. Fast 1100mV 85C Model Recovery Summary
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23. Fast 1100mV 85C Model Removal Summary
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24. Fast 1100mV 85C Model Minimum Pulse Width Summary
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25. Fast 1100mV 85C Model Metastability Summary
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26. Fast 1100mV 0C Model Setup Summary
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27. Fast 1100mV 0C Model Hold Summary
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28. Fast 1100mV 0C Model Recovery Summary
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29. Fast 1100mV 0C Model Removal Summary
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30. Fast 1100mV 0C Model Minimum Pulse Width Summary
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31. Fast 1100mV 0C Model Metastability Summary
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32. Multicorner Timing Analysis Summary
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33. Board Trace Model Assignments
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34. Input Transition Times
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35. Signal Integrity Metrics (Slow 1100mv 0c Model)
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36. Signal Integrity Metrics (Slow 1100mv 85c Model)
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37. Signal Integrity Metrics (Fast 1100mv 0c Model)
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38. Signal Integrity Metrics (Fast 1100mv 85c Model)
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39. Clock Transfers
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40. Report TCCS
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41. Report RSKM
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42. Unconstrained Paths Summary
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43. Unconstrained Input Ports
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44. Unconstrained Output Ports
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45. Unconstrained Input Ports
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46. Unconstrained Output Ports
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47. Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2025 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus Prime License Agreement,
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the Altera IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Altera and sold by Altera or its authorized distributors. Please
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refer to the Altera Software License Subscription Agreements
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on the Quartus Prime software download page.
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+---------------------------------------------------------------------------------+
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; Timing Analyzer Summary ;
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+-----------------------+---------------------------------------------------------+
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; Quartus Prime Version ; Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
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; Timing Analyzer ; Legacy Timing Analyzer ;
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; Revision Name ; asu ;
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; Device Family ; Cyclone V ;
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; Device Name ; 5CGXFC5C6F27C7 ;
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; Timing Models ; Final ;
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; Delay Model ; Combined ;
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; Rise/Fall Delays ; Enabled ;
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+-----------------------+---------------------------------------------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 2 ;
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; ; ;
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; Average used ; 1.02 ;
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; Maximum used ; 2 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 2.3% ;
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+----------------------------+-------------+
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----------
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; Clocks ;
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----------
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No clocks to report.
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--------------------------------------
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; Slow 1100mV 85C Model Fmax Summary ;
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--------------------------------------
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No paths to report.
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----------------------------------
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; Timing Closure Recommendations ;
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----------------------------------
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HTML report is unavailable in plain text report export.
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---------------------------------------
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; Slow 1100mV 85C Model Setup Summary ;
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---------------------------------------
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No paths to report.
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--------------------------------------
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; Slow 1100mV 85C Model Hold Summary ;
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--------------------------------------
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No paths to report.
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------------------------------------------
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; Slow 1100mV 85C Model Recovery Summary ;
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------------------------------------------
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No paths to report.
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-----------------------------------------
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; Slow 1100mV 85C Model Removal Summary ;
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-----------------------------------------
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No paths to report.
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-----------------------------------------------------
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; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
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-----------------------------------------------------
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No paths to report.
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-----------------------------------------------
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; Slow 1100mV 85C Model Metastability Summary ;
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-----------------------------------------------
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No synchronizer chains to report.
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-------------------------------------
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; Slow 1100mV 0C Model Fmax Summary ;
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-------------------------------------
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No paths to report.
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--------------------------------------
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; Slow 1100mV 0C Model Setup Summary ;
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--------------------------------------
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No paths to report.
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-------------------------------------
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; Slow 1100mV 0C Model Hold Summary ;
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-------------------------------------
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No paths to report.
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-----------------------------------------
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; Slow 1100mV 0C Model Recovery Summary ;
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-----------------------------------------
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No paths to report.
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----------------------------------------
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; Slow 1100mV 0C Model Removal Summary ;
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----------------------------------------
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No paths to report.
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----------------------------------------------------
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; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
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----------------------------------------------------
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No paths to report.
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----------------------------------------------
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; Slow 1100mV 0C Model Metastability Summary ;
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----------------------------------------------
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No synchronizer chains to report.
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---------------------------------------
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; Fast 1100mV 85C Model Setup Summary ;
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---------------------------------------
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No paths to report.
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--------------------------------------
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; Fast 1100mV 85C Model Hold Summary ;
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--------------------------------------
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No paths to report.
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------------------------------------------
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; Fast 1100mV 85C Model Recovery Summary ;
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------------------------------------------
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No paths to report.
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-----------------------------------------
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; Fast 1100mV 85C Model Removal Summary ;
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-----------------------------------------
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No paths to report.
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-----------------------------------------------------
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; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
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-----------------------------------------------------
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No paths to report.
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-----------------------------------------------
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; Fast 1100mV 85C Model Metastability Summary ;
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-----------------------------------------------
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No synchronizer chains to report.
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--------------------------------------
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; Fast 1100mV 0C Model Setup Summary ;
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--------------------------------------
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No paths to report.
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-------------------------------------
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; Fast 1100mV 0C Model Hold Summary ;
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-------------------------------------
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No paths to report.
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-----------------------------------------
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; Fast 1100mV 0C Model Recovery Summary ;
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-----------------------------------------
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No paths to report.
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----------------------------------------
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; Fast 1100mV 0C Model Removal Summary ;
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----------------------------------------
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No paths to report.
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----------------------------------------------------
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; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
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----------------------------------------------------
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No paths to report.
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----------------------------------------------
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; Fast 1100mV 0C Model Metastability Summary ;
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----------------------------------------------
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No synchronizer chains to report.
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+----------------------------------------------------------------------------+
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; Multicorner Timing Analysis Summary ;
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+------------------+-------+------+----------+---------+---------------------+
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; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
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+------------------+-------+------+----------+---------+---------------------+
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; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
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; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
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+------------------+-------+------+----------+---------+---------------------+
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Board Trace Model Assignments ;
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+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
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+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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; OUT_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; COUT[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; OUT_CIN[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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+------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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+----------------------------------------------------------+
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; Input Transition Times ;
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+-------+--------------+-----------------+-----------------+
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; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
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+-------+--------------+-----------------+-----------------+
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; op[0] ; 1.2 V ; 960 ps ; 960 ps ;
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; A[3] ; 1.2 V ; 960 ps ; 960 ps ;
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; B[3] ; 1.2 V ; 960 ps ; 960 ps ;
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; B[0] ; 1.2 V ; 960 ps ; 960 ps ;
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; A[0] ; 1.2 V ; 960 ps ; 960 ps ;
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; A[1] ; 1.2 V ; 960 ps ; 960 ps ;
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; B[1] ; 1.2 V ; 960 ps ; 960 ps ;
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; A[2] ; 1.2 V ; 960 ps ; 960 ps ;
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; B[2] ; 1.2 V ; 960 ps ; 960 ps ;
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+-------+--------------+-----------------+-----------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
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+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
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+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
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; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
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; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
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; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
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; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
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; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
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+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
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+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
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+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
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; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
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; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
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; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
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; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
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; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
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+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
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+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
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+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
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; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
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; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
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; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
|
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
|
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
|
|
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
|
|
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
|
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
|
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
|
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
|
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
|
; COUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
|
; OUT_CIN[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
|
|
+------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
|
|
|
|
-------------------
|
|
; Clock Transfers ;
|
|
-------------------
|
|
Nothing to report.
|
|
|
|
|
|
---------------
|
|
; Report TCCS ;
|
|
---------------
|
|
No dedicated SERDES Transmitter circuitry present in device or used in design
|
|
|
|
|
|
---------------
|
|
; Report RSKM ;
|
|
---------------
|
|
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
|
|
|
|
|
+------------------------------------------------+
|
|
; Unconstrained Paths Summary ;
|
|
+---------------------------------+-------+------+
|
|
; Property ; Setup ; Hold ;
|
|
+---------------------------------+-------+------+
|
|
; Illegal Clocks ; 0 ; 0 ;
|
|
; Unconstrained Clocks ; 0 ; 0 ;
|
|
; Unconstrained Input Ports ; 9 ; 9 ;
|
|
; Unconstrained Input Port Paths ; 41 ; 41 ;
|
|
; Unconstrained Output Ports ; 6 ; 6 ;
|
|
; Unconstrained Output Port Paths ; 41 ; 41 ;
|
|
+---------------------------------+-------+------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Input Ports ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; Input Port ; Comment ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Output Ports ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; Output Port ; Comment ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Input Ports ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; Input Port ; Comment ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Output Ports ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; Output Port ; Comment ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; COUT[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; OUT_CIN[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
|
|
|
|
+--------------------------+
|
|
; Timing Analyzer Messages ;
|
|
+--------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Timing Analyzer
|
|
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
|
Info: Processing started: Wed Sep 9 14:14:48 2026
|
|
Info: Command: quartus_sta A1_Q3 -c asu
|
|
Info: qsta_default_script.tcl version: #1
|
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
|
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
|
Info (21077): Low junction temperature is 0 degrees C
|
|
Info (21077): High junction temperature is 85 degrees C
|
|
Critical Warning (332012): Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
|
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
|
Warning (332068): No clocks defined in design.
|
|
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
|
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
|
Info (332159): No clocks to report
|
|
Info: Analyzing Slow 1100mV 85C Model
|
|
Info (332140): No fmax paths to report
|
|
Info (332140): No Setup paths to report
|
|
Info (332140): No Hold paths to report
|
|
Info (332140): No Recovery paths to report
|
|
Info (332140): No Removal paths to report
|
|
Info (332140): No Minimum Pulse Width paths to report
|
|
Info: Analyzing Slow 1100mV 0C Model
|
|
Info (334003): Started post-fitting delay annotation
|
|
Info (334004): Delay annotation completed successfully
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
|
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
|
Warning (332068): No clocks defined in design.
|
|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
|
Info (332140): No fmax paths to report
|
|
Info (332140): No Setup paths to report
|
|
Info (332140): No Hold paths to report
|
|
Info (332140): No Recovery paths to report
|
|
Info (332140): No Removal paths to report
|
|
Info (332140): No Minimum Pulse Width paths to report
|
|
Info: Analyzing Fast 1100mV 85C Model
|
|
Info (334003): Started post-fitting delay annotation
|
|
Info (334004): Delay annotation completed successfully
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
|
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
|
Warning (332068): No clocks defined in design.
|
|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
|
Info (332140): No Setup paths to report
|
|
Info (332140): No Hold paths to report
|
|
Info (332140): No Recovery paths to report
|
|
Info (332140): No Removal paths to report
|
|
Info (332140): No Minimum Pulse Width paths to report
|
|
Info: Analyzing Fast 1100mV 0C Model
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
|
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
|
Warning (332068): No clocks defined in design.
|
|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
|
Info (332140): No Setup paths to report
|
|
Info (332140): No Hold paths to report
|
|
Info (332140): No Recovery paths to report
|
|
Info (332140): No Removal paths to report
|
|
Info (332140): No Minimum Pulse Width paths to report
|
|
Info (332102): Design is not fully constrained for setup requirements
|
|
Info (332102): Design is not fully constrained for hold requirements
|
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
|
|
Info: Peak virtual memory: 780 megabytes
|
|
Info: Processing ended: Wed Sep 9 14:14:53 2026
|
|
Info: Elapsed time: 00:00:05
|
|
Info: Total CPU time (on all processors): 00:00:05
|
|
|
|
|