TroubleElectrical/FPGA_Uni
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Added code to display current PC,

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Removed Blanking from 7seg 4 digits,
Changed reset to a switch rather than button
Compiled working version for board
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TroubleElectrical committed 2026-10-16 14:27:29 +11:00
1 parent 91a5090528
commit d962a1b557
199 files changed
+125133 -7192
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Quartus/A2/output_files/assignment2.fit.summary
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Fitter Status : Successful - Fri Oct 16 09:58:48 2026
Fitter Status : Successful - Fri Oct 16 14:22:59 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 1 / 29,080 ( < 1 % )
Total registers : 0
Total pins : 40 / 364 ( 11 % )
Logic utilization (in ALMs) : 1,735 / 29,080 ( 6 % )
Total registers : 2524
Total pins : 41 / 364 ( 11 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )