TroubleElectrical/FPGA_Uni
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Added code to display current PC,

Browse Source 
Removed Blanking from 7seg 4 digits,
Changed reset to a switch rather than button
Compiled working version for board
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TroubleElectrical committed 2026-10-16 14:27:29 +11:00
1 parent 91a5090528
commit d962a1b557
199 files changed
+125133 -7192
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Quartus/A2/output_files/assignment2.asm.rpt
+9 -9
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@@ -1,5 +1,5 @@
Assembler report for assignment2
Fri Oct 16 09:58:56 2026
Fri Oct 16 14:23:09 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Oct 16 09:58:56 2026 ;
; Assembler Status ; Successful - Fri Oct 16 14:23:09 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
+----------------+--------------------------+
; Option ; Setting ;
+----------------+--------------------------+
; JTAG usercode ; 0x00780AC3 ;
; Checksum ; 0x00780AC3 ;
; JTAG usercode ; 0x00BE0B15 ;
; Checksum ; 0x00BE0B15 ;
+----------------+--------------------------+
@@ -78,13 +78,13 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Fri Oct 16 09:58:50 2026
Info: Processing started: Fri Oct 16 14:23:02 2026
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 520 megabytes
Info: Processing ended: Fri Oct 16 09:58:56 2026
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05
Info: Peak virtual memory: 548 megabytes
Info: Processing ended: Fri Oct 16 14:23:09 2026
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:06
Quartus/A2/output_files/assignment2.done
+1 -1
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@@ -1 +1 @@
Fri Oct 16 09:59:05 2026
Fri Oct 16 14:23:32 2026
Quartus/A2/output_files/assignment2.eda.rpt
+7 -7
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@@ -1,5 +1,5 @@
EDA Netlist Writer report for assignment2
Fri Oct 16 09:59:05 2026
Fri Oct 16 14:23:31 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Fri Oct 16 09:59:05 2026 ;
; EDA Netlist Writer Status ; Successful - Fri Oct 16 14:23:31 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
@@ -81,13 +81,13 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Fri Oct 16 09:59:04 2026
Info: Processing started: Fri Oct 16 14:23:29 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 669 megabytes
Info: Processing ended: Fri Oct 16 09:59:05 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: Peak virtual memory: 693 megabytes
Info: Processing ended: Fri Oct 16 14:23:31 2026
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Quartus/A2/output_files/assignment2.fit.rpt
+1963 -357
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Quartus/A2/output_files/assignment2.fit.summary
+4 -4
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@@ -1,13 +1,13 @@
Fitter Status : Successful - Fri Oct 16 09:58:48 2026
Fitter Status : Successful - Fri Oct 16 14:22:59 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 1 / 29,080 ( < 1 % )
Total registers : 0
Total pins : 40 / 364 ( 11 % )
Logic utilization (in ALMs) : 1,735 / 29,080 ( 6 % )
Total registers : 2524
Total pins : 41 / 364 ( 11 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )
Quartus/A2/output_files/assignment2.flow.rpt
+13 -13
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@@ -1,5 +1,5 @@
Flow report for assignment2
Fri Oct 16 09:59:05 2026
Fri Oct 16 14:23:31 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,16 +41,16 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Fri Oct 16 09:59:05 2026 ;
; Flow Status ; Successful - Fri Oct 16 14:23:31 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 40 / 364 ( 11 % ) ;
; Logic utilization (in ALMs) ; 1,735 / 29,080 ( 6 % ) ;
; Total registers ; 2524 ;
; Total pins ; 41 / 364 ( 11 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/16/2026 09:58:06 ;
; Start date & time ; 10/16/2026 14:20:44 ;
; Main task ; Compilation ;
; Revision Name ; assignment2 ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 231344018423319.179210508627966 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 248825844801641.179212084341235 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -103,12 +103,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 427 MB ; 00:00:26 ;
; Fitter ; 00:00:28 ; 1.0 ; 1336 MB ; 00:00:38 ;
; Assembler ; 00:00:06 ; 1.0 ; 520 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 765 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 669 MB ; 00:00:01 ;
; Total ; 00:00:52 ; -- ; -- ; 00:01:15 ;
; Analysis & Synthesis ; 00:00:19 ; 1.0 ; 448 MB ; 00:00:32 ;
; Fitter ; 00:01:55 ; 1.1 ; 1435 MB ; 00:02:51 ;
; Assembler ; 00:00:07 ; 1.0 ; 548 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:17 ; 1.6 ; 854 MB ; 00:00:27 ;
; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 693 MB ; 00:00:02 ;
; Total ; 00:02:40 ; -- ; -- ; 00:03:58 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
Quartus/A2/output_files/assignment2.map.rpt
+488 -5739
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Quartus/A2/output_files/assignment2.map.summary
+3 -3
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@@ -1,11 +1,11 @@
Analysis & Synthesis Status : Successful - Fri Oct 16 09:58:19 2026
Analysis & Synthesis Status : Successful - Fri Oct 16 14:21:03 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 40
Total registers : 2302
Total pins : 41
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
Quartus/A2/output_files/assignment2.pin
+9 -9
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@@ -160,7 +160,7 @@ GND : AC5 : gnd : :
VCCIO3A : AC6 : power : : 2.5V : 3A :
VREFB3AN0 : AC7 : power : : : 3A :
HID_Hi_Low[0] : AC8 : input : 1.2 V : : 3B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3B :
rst[0] : AC9 : input : 1.2 V : : 3B : Y
HID_Register[2] : AC10 : input : 1.2 V : : 3B : Y
GND : AC11 : gnd : : : :
VREFB3BN0 : AC12 : power : : : 3B :
@@ -312,7 +312,7 @@ GND : D3 : gnd : :
GND : D4 : gnd : : : :
nCE : D5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
out_seg_1[0] : D7 : output : 2.5 V : : 8A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8A :
VCCIO8A : D9 : power : : 2.5V : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 7A :
@@ -363,8 +363,8 @@ NC : F2 : : :
GND : F3 : gnd : : : :
GND : F4 : gnd : : : :
nCONFIG : F5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8A :
out_seg_1[0] : F6 : output : 2.5 V : : 8A : Y
out_seg_0[0] : F7 : output : 2.5 V : : 8A : Y
VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : :
VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A :
GND : F10 : gnd : : : :
@@ -389,8 +389,8 @@ GND : G2 : gnd : :
NC : G3 : : : : :
NC : G4 : : : : :
GND : G5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
out_seg_2[0] : G6 : output : 2.5 V : : 8A : Y
out_seg_3[0] : G7 : output : 2.5 V : : 8A : Y
VCCIO8A : G8 : power : : 2.5V : 8A :
VCC_AUX : G9 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
@@ -423,11 +423,11 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : :
VCCIO7A : H11 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7A :
out_seg_3[0] : H14 : output : 2.5 V : : 7A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7A :
GND : H16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7A :
out_seg_2[0] : H18 : output : 2.5 V : : 7A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6A :
VCCIO6A : H21 : power : : 2.5V : 6A :
@@ -460,7 +460,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : :
VCCPD6A : J22 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
VCCIO6A : J24 : power : : 2.5V : 6A :
out_seg_0[0] : J25 : output : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
GXB_NC : K1 : : : : B1L :
GXB_NC : K2 : : : : B1L :
Quartus/A2/output_files/assignment2.sof
BIN
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Quartus/A2/output_files/assignment2.sta.rpt
+339 -124
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@@ -1,5 +1,5 @@
Timing Analyzer report for assignment2
Fri Oct 16 09:59:02 2026
Fri Oct 16 14:23:28 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -44,11 +44,17 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
36. Signal Integrity Metrics (Slow 1100mv 85c Model)
37. Signal Integrity Metrics (Fast 1100mv 0c Model)
38. Signal Integrity Metrics (Fast 1100mv 85c Model)
39. Clock Transfers
40. Report TCCS
41. Report RSKM
42. Unconstrained Paths Summary
43. Timing Analyzer Messages
39. Setup Transfers
40. Hold Transfers
41. Report TCCS
42. Report RSKM
43. Unconstrained Paths Summary
44. Clock Status Summary
45. Unconstrained Input Ports
46. Unconstrained Output Ports
47. Unconstrained Input Ports
48. Unconstrained Output Ports
49. Timing Analyzer Messages
@@ -94,25 +100,32 @@ on the Quartus Prime software download page.
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Average used ; 1.58 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.0% ;
; Processor 2 ; 58.5% ;
+----------------------------+-------------+
----------
; Clocks ;
----------
No clocks to report.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
; clk[0] ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk[0] } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
--------------------------------------
; Slow 1100mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.
+-------------------------------------------------+
; Slow 1100mV 85C Model Fmax Summary ;
+-----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 62.97 MHz ; 62.97 MHz ; clk[0] ; ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
@@ -121,16 +134,22 @@ No paths to report.
HTML report is unavailable in plain text report export.
---------------------------------------
+-------------------------------------+
; Slow 1100mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
+--------+---------+------------------+
; Clock ; Slack ; End Point TNS ;
+--------+---------+------------------+
; clk[0] ; -14.881 ; -27730.277 ;
+--------+---------+------------------+
--------------------------------------
+------------------------------------+
; Slow 1100mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
+--------+-------+-------------------+
; Clock ; Slack ; End Point TNS ;
+--------+-------+-------------------+
; clk[0] ; 0.262 ; 0.000 ;
+--------+-------+-------------------+
------------------------------------------
@@ -145,10 +164,13 @@ No paths to report.
No paths to report.
-----------------------------------------------------
+---------------------------------------------------+
; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
+--------+--------+---------------------------------+
; Clock ; Slack ; End Point TNS ;
+--------+--------+---------------------------------+
; clk[0] ; -0.538 ; -1978.741 ;
+--------+--------+---------------------------------+
-----------------------------------------------
@@ -157,22 +179,32 @@ No paths to report.
No synchronizer chains to report.
-------------------------------------
; Slow 1100mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.
+-------------------------------------------------+
; Slow 1100mV 0C Model Fmax Summary ;
+-----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 64.35 MHz ; 64.35 MHz ; clk[0] ; ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
--------------------------------------
+------------------------------------+
; Slow 1100mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
+--------+---------+-----------------+
; Clock ; Slack ; End Point TNS ;
+--------+---------+-----------------+
; clk[0] ; -14.540 ; -27019.196 ;
+--------+---------+-----------------+
-------------------------------------
+-----------------------------------+
; Slow 1100mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
+--------+-------+------------------+
; Clock ; Slack ; End Point TNS ;
+--------+-------+------------------+
; clk[0] ; 0.245 ; 0.000 ;
+--------+-------+------------------+
-----------------------------------------
@@ -187,10 +219,13 @@ No paths to report.
No paths to report.
----------------------------------------------------
+--------------------------------------------------+
; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
+--------+--------+--------------------------------+
; Clock ; Slack ; End Point TNS ;
+--------+--------+--------------------------------+
; clk[0] ; -0.538 ; -2025.649 ;
+--------+--------+--------------------------------+
----------------------------------------------
@@ -199,16 +234,22 @@ No paths to report.
No synchronizer chains to report.
---------------------------------------
+-------------------------------------+
; Fast 1100mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
+--------+--------+-------------------+
; Clock ; Slack ; End Point TNS ;
+--------+--------+-------------------+
; clk[0] ; -7.846 ; -13963.900 ;
+--------+--------+-------------------+
--------------------------------------
+------------------------------------+
; Fast 1100mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
+--------+-------+-------------------+
; Clock ; Slack ; End Point TNS ;
+--------+-------+-------------------+
; clk[0] ; 0.135 ; 0.000 ;
+--------+-------+-------------------+
------------------------------------------
@@ -223,10 +264,13 @@ No paths to report.
No paths to report.
-----------------------------------------------------
+---------------------------------------------------+
; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
+--------+-------+----------------------------------+
; Clock ; Slack ; End Point TNS ;
+--------+-------+----------------------------------+
; clk[0] ; 0.016 ; 0.000 ;
+--------+-------+----------------------------------+
-----------------------------------------------
@@ -235,16 +279,22 @@ No paths to report.
No synchronizer chains to report.
--------------------------------------
+------------------------------------+
; Fast 1100mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
+--------+--------+------------------+
; Clock ; Slack ; End Point TNS ;
+--------+--------+------------------+
; clk[0] ; -6.879 ; -12147.650 ;
+--------+--------+------------------+
-------------------------------------
+-----------------------------------+
; Fast 1100mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
+--------+-------+------------------+
; Clock ; Slack ; End Point TNS ;
+--------+-------+------------------+
; clk[0] ; 0.123 ; 0.000 ;
+--------+-------+------------------+
-----------------------------------------
@@ -259,10 +309,13 @@ No paths to report.
No paths to report.
----------------------------------------------------
+--------------------------------------------------+
; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
+--------+-------+---------------------------------+
; Clock ; Slack ; End Point TNS ;
+--------+-------+---------------------------------+
; clk[0] ; 0.015 ; 0.000 ;
+--------+-------+---------------------------------+
----------------------------------------------
@@ -271,14 +324,16 @@ No paths to report.
No synchronizer chains to report.
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+------------------+-------+------+----------+---------+---------------------+
+----------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+------------+-------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+------------+-------+----------+---------+---------------------+
; Worst-case Slack ; -14.881 ; 0.123 ; N/A ; N/A ; -0.538 ;
; clk[0] ; -14.881 ; 0.123 ; N/A ; N/A ; -0.538 ;
; Design-wide TNS ; -27730.277 ; 0.0 ; 0.0 ; 0.0 ; -2025.649 ;
; clk[0] ; -27730.277 ; 0.000 ; N/A ; N/A ; -2025.649 ;
+------------------+------------+-------+----------+---------+---------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -326,14 +381,15 @@ No synchronizer chains to report.
+-----------------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-----------------+--------------+-----------------+-----------------+
; HID_PC[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Hi_Low[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[4] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[3] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[1] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[2] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[0] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[1] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_Register[3] ; 1.2 V ; 960 ps ; 960 ps ;
; HID_PC[0] ; 1.2 V ; 960 ps ; 960 ps ;
; clk[0] ; 1.2 V ; 960 ps ; 960 ps ;
; rst[0] ; 1.2 V ; 960 ps ; 960 ps ;
+-----------------+--------------+-----------------+-----------------+
@@ -342,7 +398,7 @@ No synchronizer chains to report.
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
@@ -358,7 +414,7 @@ No synchronizer chains to report.
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
@@ -366,7 +422,7 @@ No synchronizer chains to report.
; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
@@ -382,7 +438,7 @@ No synchronizer chains to report.
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
@@ -398,7 +454,7 @@ No synchronizer chains to report.
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ;
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ;
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ;
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
@@ -406,7 +462,7 @@ No synchronizer chains to report.
; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
@@ -422,7 +478,7 @@ No synchronizer chains to report.
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
@@ -438,7 +494,7 @@ No synchronizer chains to report.
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
@@ -446,7 +502,7 @@ No synchronizer chains to report.
; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
@@ -462,7 +518,7 @@ No synchronizer chains to report.
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; out_seg_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; out_seg_0[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
; out_seg_0[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
; out_seg_0[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
@@ -478,7 +534,7 @@ No synchronizer chains to report.
; out_seg_1[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
; out_seg_1[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
; out_seg_1[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; out_seg_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; out_seg_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; out_seg_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; out_seg_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
@@ -486,7 +542,7 @@ No synchronizer chains to report.
; out_seg_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
; out_seg_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
; out_seg_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
; out_seg_3[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; out_seg_3[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
; out_seg_3[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
; out_seg_3[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
@@ -497,10 +553,24 @@ No synchronizer chains to report.
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
+--------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+-----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+-----------+----------+----------+----------+
; clk[0] ; clk[0] ; 359099286 ; 0 ; 0 ; 0 ;
+------------+----------+-----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+-----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+-----------+----------+----------+----------+
; clk[0] ; clk[0] ; 359099286 ; 0 ; 0 ; 0 ;
+------------+----------+-----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
@@ -522,20 +592,133 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 0 ; 0 ;
; Unconstrained Input Port Paths ; 0 ; 0 ;
; Unconstrained Output Ports ; 0 ; 0 ;
; Unconstrained Output Port Paths ; 0 ; 0 ;
; Unconstrained Input Ports ; 8 ; 8 ;
; Unconstrained Input Port Paths ; 1522 ; 1522 ;
; Unconstrained Output Ports ; 28 ; 28 ;
; Unconstrained Output Port Paths ; 7350 ; 7350 ;
+---------------------------------+-------+------+
+--------------------------------------+
; Clock Status Summary ;
+--------+--------+------+-------------+
; Target ; Clock ; Type ; Status ;
+--------+--------+------+-------------+
; clk[0] ; clk[0] ; Base ; Constrained ;
+--------+--------+------+-------------+
+--------------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+-----------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+-----------------+--------------------------------------------------------------------------------------+
; HID_Hi_Low[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_PC[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_Register[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_Register[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_Register[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_Register[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_Register[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; rst[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-----------------+--------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+--------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+--------------+---------------------------------------------------------------------------------------+
; out_seg_0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+--------------+---------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+-----------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+-----------------+--------------------------------------------------------------------------------------+
; HID_Hi_Low[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_PC[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_Register[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_Register[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_Register[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_Register[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HID_Register[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; rst[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-----------------+--------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+--------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+--------------+---------------------------------------------------------------------------------------+
; out_seg_0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_0[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_2[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; out_seg_3[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+--------------+---------------------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Fri Oct 16 09:58:57 2026
Info: Processing started: Fri Oct 16 14:23:10 2026
Info: Command: quartus_sta assignment2 -c assignment2
Info: qsta_default_script.tcl version: #1
Info (20032): Parallel compilation is enabled and will use up to 2 processors
@@ -543,60 +726,92 @@ Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name clk[0] clk[0]
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1100mV 85C Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -14.881
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -14.881 -27730.277 clk[0]
Info (332146): Worst-case hold slack is 0.262
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.262 0.000 clk[0]
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332146): Worst-case minimum pulse width slack is -0.538
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -0.538 -1978.741 clk[0]
Info: Analyzing Slow 1100mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -14.540
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -14.540 -27019.196 clk[0]
Info (332146): Worst-case hold slack is 0.245
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.245 0.000 clk[0]
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332146): Worst-case minimum pulse width slack is -0.538
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -0.538 -2025.649 clk[0]
Info: Analyzing Fast 1100mV 85C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -7.846
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -7.846 -13963.900 clk[0]
Info (332146): Worst-case hold slack is 0.135
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.135 0.000 clk[0]
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332146): Worst-case minimum pulse width slack is 0.016
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.016 0.000 clk[0]
Info: Analyzing Fast 1100mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -6.879
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -6.879 -12147.650 clk[0]
Info (332146): Worst-case hold slack is 0.123
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.123 0.000 clk[0]
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332101): Design is fully constrained for setup requirements
Info (332101): Design is fully constrained for hold requirements
Info (332146): Worst-case minimum pulse width slack is 0.015
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.015 0.000 clk[0]
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 765 megabytes
Info: Processing ended: Fri Oct 16 09:59:02 2026
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05
Info: Peak virtual memory: 854 megabytes
Info: Processing ended: Fri Oct 16 14:23:28 2026
Info: Elapsed time: 00:00:18
Info: Total CPU time (on all processors): 00:00:27
Quartus/A2/output_files/assignment2.sta.summary
+48
View File
@@ -2,4 +2,52 @@
Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1100mV 85C Model Setup 'clk[0]'
Slack : -14.881
TNS : -27730.277
Type : Slow 1100mV 85C Model Hold 'clk[0]'
Slack : 0.262
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk[0]'
Slack : -0.538
TNS : -1978.741
Type : Slow 1100mV 0C Model Setup 'clk[0]'
Slack : -14.540
TNS : -27019.196
Type : Slow 1100mV 0C Model Hold 'clk[0]'
Slack : 0.245
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk[0]'
Slack : -0.538
TNS : -2025.649
Type : Fast 1100mV 85C Model Setup 'clk[0]'
Slack : -7.846
TNS : -13963.900
Type : Fast 1100mV 85C Model Hold 'clk[0]'
Slack : 0.135
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk[0]'
Slack : 0.016
TNS : 0.000
Type : Fast 1100mV 0C Model Setup 'clk[0]'
Slack : -6.879
TNS : -12147.650
Type : Fast 1100mV 0C Model Hold 'clk[0]'
Slack : 0.123
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk[0]'
Slack : 0.015
TNS : 0.000
------------------------------------------------------------