Added code to display current PC,
Removed Blanking from 7seg 4 digits, Changed reset to a switch rather than button Compiled working version for board
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@@ -1,37 +1,34 @@
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792105086550 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792105086551 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 16 09:58:06 2026 " "Processing started: Fri Oct 16 09:58:06 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792105086551 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792105086551 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792105086551 ""}
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{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792105086872 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 14 14 " "Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "6 control_unit " "Found entity 6: control_unit" { } { { "../../modules/control_unit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "11 sign_extender " "Found entity 11: sign_extender" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg " "Found entity 12: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "13 seven_seg_4digit " "Found entity 13: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} { "Info" "ISGN_ENTITY_NAME" "14 assignment2 " "Found entity 14: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792105095944 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792105095944 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792105096087 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 assignment2.sv(87) " "Verilog HDL assignment warning at assignment2.sv(87): truncated value with size 32 to match size of target (10)" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 87 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792105096098 "|assignment2"}
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "flags\[2\] 0 assignment2.sv(48) " "Net \"flags\[2\]\" at assignment2.sv(48) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 48 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792105096098 "|assignment2"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096099 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 57 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096107 ""}
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{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1792105096118 "|assignment2|rom:ROM"}
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792105096162 "|assignment2|rom:ROM"}
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792105096162 "|assignment2|rom:ROM"}
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792105096162 "|assignment2|rom:ROM"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram ram:RAM " "Elaborating entity \"ram\" for hierarchy \"ram:RAM\"" { } { { "../../modules/assignment2.sv" "RAM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 60 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096167 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 2 ram.sv(18) " "Verilog HDL assignment warning at ram.sv(18): truncated value with size 8 to match size of target (2)" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792105096168 "|assignment2|ram:RAM"}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 ram.sv(24) " "Verilog HDL assignment warning at ram.sv(24): truncated value with size 32 to match size of target (2)" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792105096915 "|assignment2|ram:RAM"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_unit control_unit:CONTROL_UNIT " "Elaborating entity \"control_unit\" for hierarchy \"control_unit:CONTROL_UNIT\"" { } { { "../../modules/assignment2.sv" "CONTROL_UNIT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 64 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096923 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 control_unit.sv(29) " "Verilog HDL assignment warning at control_unit.sv(29): truncated value with size 6 to match size of target (4)" { } { { "../../modules/control_unit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 29 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792105096924 "|assignment2|control_unit:CONTROL_UNIT"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier control_unit:CONTROL_UNIT\|instruction_classifier:CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"control_unit:CONTROL_UNIT\|instruction_classifier:CLASSIFIER\"" { } { { "../../modules/control_unit.sv" "CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 23 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096928 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 73 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105096932 ""}
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{ "Warning" "WVRFX_VERI_2116_UNCONVERTED" "regs register_file.sv(14) " "Verilog HDL warning at register_file.sv(14): initial value for variable regs should be constant" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 14 0 0 } } } 0 10855 "Verilog HDL warning at %2!s!: initial value for variable %1!s! should be constant" 0 0 "Analysis & Synthesis" 0 -1 1792105096934 "|assignment2|register_file:REGS"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_extender sign_extender:SIGNEXT " "Elaborating entity \"sign_extender\" for hierarchy \"sign_extender:SIGNEXT\"" { } { { "../../modules/assignment2.sv" "SIGNEXT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 76 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097052 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097055 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097062 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097068 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg_4digit seven_seg_4digit:display " "Elaborating entity \"seven_seg_4digit\" for hierarchy \"seven_seg_4digit:display\"" { } { { "../../modules/assignment2.sv" "display" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 104 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097074 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg_4digit:display\|seven_seg:digit0 " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg_4digit:display\|seven_seg:digit0\"" { } { { "../../modules/seven_seg_4digit.sv" "digit0" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105097077 ""}
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{ "Info" "IINFER_UNINFERRED_RAM_SUMMARY" "1 " "Found 1 instances of uninferred RAM logic" { { "Info" "IINFER_READ_LOGIC_IS_ASYNCHRONOUS" "ram:RAM\|mem " "RAM logic \"ram:RAM\|mem\" is uninferred due to asynchronous read logic" { } { { "../../modules/ram.sv" "mem" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 13 -1 0 } } } 0 276007 "RAM logic \"%1!s!\" is uninferred due to asynchronous read logic" 0 0 "Design Software" 0 -1 1792105097741 ""} } { } 0 276014 "Found %1!d! instances of uninferred RAM logic" 0 0 "Analysis & Synthesis" 0 -1 1792105097741 ""}
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{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/db/assignment2.ram0_rom_d8639f5.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/db/assignment2.ram0_rom_d8639f5.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" { } { } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1792105097774 ""}
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{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1792105098851 ""}
|
||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[0\] VCC " "Pin \"out_seg_0\[0\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[1\] VCC " "Pin \"out_seg_0\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[2\] VCC " "Pin \"out_seg_0\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[3\] VCC " "Pin \"out_seg_0\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[4\] VCC " "Pin \"out_seg_0\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[5\] VCC " "Pin \"out_seg_0\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[6\] VCC " "Pin \"out_seg_0\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[7\] VCC " "Pin \"out_seg_0\[7\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_0[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[0\] VCC " "Pin \"out_seg_1\[0\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[1\] VCC " "Pin \"out_seg_1\[1\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[2\] VCC " "Pin \"out_seg_1\[2\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[3\] VCC " "Pin \"out_seg_1\[3\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[4\] VCC " "Pin \"out_seg_1\[4\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[5\] VCC " "Pin \"out_seg_1\[5\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792105098866 "|assignment2|out_seg_1[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[6\] VCC " "Pin \"out_seg_1\[6\]\" is stuck at VCC" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGLine truncated
|
||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "30 " "30 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1792105098892 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1792105099101 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792105099101 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_PC\[0\] " "No output dependent on input pin \"HID_PC\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 20 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_PC[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Hi_Low\[0\] " "No output dependent on input pin \"HID_Hi_Low\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 21 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Hi_Low[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[4\] " "No output dependent on input pin \"HID_Register\[4\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Register[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[2\] " "No output dependent on input pin \"HID_Register\[2\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Register[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[0\] " "No output dependent on input pin \"HID_Register\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Register[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[1\] " "No output dependent on input pin \"HID_Register\[1\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Register[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "HID_Register\[3\] " "No output dependent on input pin \"HID_Register\[3\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|HID_Register[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1792105099207 "|assignment2|clk[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1792105099207 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1792105099208 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1792105099208 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1792105099208 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 54 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 54 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "440 " "Peak virtual memory: 440 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792105099231 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 16 09:58:19 2026 " "Processing ended: Fri Oct 16 09:58:19 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792105099231 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792105099231 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792105099231 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792105099231 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1792120843779 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1792120843779 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 16 14:20:43 2026 " "Processing started: Fri Oct 16 14:20:43 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1792120843779 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792120843779 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792120843780 ""}
|
||||
{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "2 " "Parallel compilation is enabled and will use up to 2 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1792120844142 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 14 14 " "Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "6 control_unit " "Found entity 6: control_unit" { } { { "../../modules/control_unit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 10 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "11 sign_extender " "Found entity 11: sign_extender" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "12 seven_seg " "Found entity 12: seven_seg" { } { { "../../modules/seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "13 seven_seg_4digit " "Found entity 13: seven_seg_4digit" { } { { "../../modules/seven_seg_4digit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} { "Info" "ISGN_ENTITY_NAME" "14 assignment2 " "Found entity 14: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1792120853036 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1792120853036 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1792120853196 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853203 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853238 ""}
|
||||
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1792120853247 "|assignment2|rom:ROM"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792120853273 "|assignment2|rom:ROM"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792120853273 "|assignment2|rom:ROM"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1792120853274 "|assignment2|rom:ROM"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram ram:RAM " "Elaborating entity \"ram\" for hierarchy \"ram:RAM\"" { } { { "../../modules/assignment2.sv" "RAM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 64 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853279 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 ram.sv(24) " "Verilog HDL assignment warning at ram.sv(24): truncated value with size 32 to match size of target (5)" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792120853384 "|assignment2|ram:RAM"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_unit control_unit:CONTROL_UNIT " "Elaborating entity \"control_unit\" for hierarchy \"control_unit:CONTROL_UNIT\"" { } { { "../../modules/assignment2.sv" "CONTROL_UNIT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 68 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853600 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 1 control_unit.sv(26) " "Verilog HDL assignment warning at control_unit.sv(26): truncated value with size 6 to match size of target (1)" { } { { "../../modules/control_unit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 26 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792120853601 "|assignment2|control_unit:CONTROL_UNIT"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 1 control_unit.sv(27) " "Verilog HDL assignment warning at control_unit.sv(27): truncated value with size 6 to match size of target (1)" { } { { "../../modules/control_unit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 27 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792120853601 "|assignment2|control_unit:CONTROL_UNIT"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 control_unit.sv(29) " "Verilog HDL assignment warning at control_unit.sv(29): truncated value with size 8 to match size of target (4)" { } { { "../../modules/control_unit.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 29 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792120853601 "|assignment2|control_unit:CONTROL_UNIT"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier control_unit:CONTROL_UNIT\|instruction_classifier:CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"control_unit:CONTROL_UNIT\|instruction_classifier:CLASSIFIER\"" { } { { "../../modules/control_unit.sv" "CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/control_unit.sv" 23 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853604 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 77 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853608 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_extender sign_extender:SIGNEXT " "Elaborating entity \"sign_extender\" for hierarchy \"sign_extender:SIGNEXT\"" { } { { "../../modules/assignment2.sv" "SIGNEXT" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853719 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 1 sign_extender.sv(10) " "Verilog HDL assignment warning at sign_extender.sv(10): truncated value with size 16 to match size of target (1)" { } { { "../../modules/sign_extender.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv" 10 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1792120853719 "|assignment2|sign_extender:SIGNEXT"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 82 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853725 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853733 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853746 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg_4digit seven_seg_4digit:display " "Elaborating entity \"seven_seg_4digit\" for hierarchy \"seven_seg_4digit:display\"" { } { { "../../modules/assignment2.sv" "display" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 110 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853752 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg_4digit:display\|seven_seg:digit0 " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg_4digit:display\|seven_seg:digit0\"" { } { { "../../modules/seven_seg_4digit.sv" "digit0" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120853755 ""}
|
||||
{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/db/assignment2.ram0_rom_a404080c.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/db/assignment2.ram0_rom_a404080c.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" { } { } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1792120854747 ""}
|
||||
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1792120857467 ""}
|
||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_0\[0\] GND " "Pin \"out_seg_0\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792120859843 "|assignment2|out_seg_0[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_1\[0\] GND " "Pin \"out_seg_1\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792120859843 "|assignment2|out_seg_1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_2\[0\] GND " "Pin \"out_seg_2\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792120859843 "|assignment2|out_seg_2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "out_seg_3\[0\] GND " "Pin \"out_seg_3\[0\]\" is stuck at GND" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1792120859843 "|assignment2|out_seg_3[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1792120859843 ""}
|
||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1792120860125 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1792120863166 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1792120863166 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "4331 " "Implemented 4331 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1792120863479 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1792120863479 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4290 " "Implemented 4290 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1792120863479 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1792120863479 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "465 " "Peak virtual memory: 465 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1792120863495 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 16 14:21:03 2026 " "Processing ended: Fri Oct 16 14:21:03 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1792120863495 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Elapsed time: 00:00:20" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1792120863495 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:33 " "Total CPU time (on all processors): 00:00:33" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1792120863495 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1792120863495 ""}
|
||||
Reference in new issue
Block a user