Updated ram.sv to resolve compilation error

modules/ram.sv

@@ -10,7 +10,7 @@ module ram #(addrwidth=9, datawidth=5)(
 );
 
     // TODO: Make this byte-sized, NOT word-sized!
-    logic [2**width-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
+    logic [2**datawidth-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
 
     // NOTE: Possible issue with assignments still pending by end of initial block
     initial begin