From cdde70e6c2392dc290acd4f2a3881e596425666d Mon Sep 17 00:00:00 2001
From: TroubleElectrical <c3428958@uon.edu.au>
Date: Thu, 15 Oct 2026 15:42:26 +1100
Subject: [PATCH] Updated ram.sv to resolve compilation error

---
 modules/ram.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/modules/ram.sv b/modules/ram.sv
index 9266519..eaddf77 100644
--- a/modules/ram.sv
+++ b/modules/ram.sv
@@ -10,7 +10,7 @@ module ram #(addrwidth=9, datawidth=5)(
 );
 
     // TODO: Make this byte-sized, NOT word-sized!
-    logic [2**width-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
+    logic [2**datawidth-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
 
     // NOTE: Possible issue with assignments still pending by end of initial block
     initial begin