TroubleElectrical/FPGA_Uni
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Implemented instruction classifier on board (Q6) and added blank submission files (for now)

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TroubleElectrical committed 2026-09-15 20:00:35 +10:00
1 parent 9583abd307
commit c27a04ef73
128 files changed
+1487 -1376
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Quartus/A1_Q6/output_files/instruction_classifier.flow.rpt
+10 -10
View File
@@ -1,5 +1,5 @@
Flow report for instruction_classifier
Tue Sep 15 10:20:23 2026
Tue Sep 15 19:57:36 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Sep 15 10:20:23 2026 ;
; Flow Status ; Successful - Tue Sep 15 19:57:36 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; instruction_classifier ;
; Top-level Entity Name ; instruction_classifier ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+------------------------+
; Option ; Setting ;
+-------------------+------------------------+
; Start date & time ; 09/15/2026 10:19:22 ;
; Start date & time ; 09/15/2026 19:56:40 ;
; Main task ; Compilation ;
; Revision Name ; instruction_classifier ;
+-------------------+------------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 253029099468756.178943156207722 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 268883478169649.178946620008468 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 413 MB ; 00:00:26 ;
; Fitter ; 00:00:32 ; 1.0 ; 1369 MB ; 00:00:48 ;
; Assembler ; 00:00:06 ; 1.0 ; 517 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 785 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 659 MB ; 00:00:01 ;
; Total ; 00:00:56 ; -- ; -- ; 00:01:26 ;
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:27 ;
; Fitter ; 00:00:28 ; 1.0 ; 1384 MB ; 00:00:39 ;
; Assembler ; 00:00:05 ; 1.0 ; 513 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 776 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:00:50 ; -- ; -- ; 00:01:17 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+